mb/lenovo: Add ThinkPad W530 support

Tested and working:
  - Wi-Fi
  - Ethernet
  - WWAN ? (interface is created in linux, didn't actually test it, should work)
  - Bluetooth
  - Speakers
  - Internal mic
  - SD card reader
  - Suspend and resume
  - Keyboard, touchpad, trackpoint
  - Fan
  - Webcam
  - 4 RAM slots
  - All USB ports
  - mSATA
  - VGA ROM (FIXME: black screen after resume from s3)
  - Native graphics initialization (FIXME: probably incorrect panel frequency, etc. in GRUB; in linux everything's fine incl. resume from s3)
  - libgfxinit
  - GRUB payload
  - SeaBIOS payload
  - Internal flashing using flashrom

Not tested yet:
  - Fingerprint reader
  - Colorimeter
  - Smart card reader
  - Docking station
  - VGA output
  - Optical disc drive
  - Discrete graphics

TODO:
  - Test BDC detection

Change-Id: Ic7918ea18712221cc62c5564caede340f71ce400
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Reviewed-on: https://review.coreboot.org/26136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig
index de867c2..93ec83b 100644
--- a/src/mainboard/lenovo/t530/Kconfig
+++ b/src/mainboard/lenovo/t530/Kconfig
@@ -1,7 +1,5 @@
-if BOARD_LENOVO_T530
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
+config BOARD_LENOVO_BASEBOARD_T530
+	def_bool n
 	select SYSTEM_TYPE_LAPTOP
 	select CPU_INTEL_SOCKET_RPGA989
 	select NORTHBRIDGE_INTEL_IVYBRIDGE
@@ -21,9 +19,14 @@
 	select MAINBOARD_HAS_LPC_TPM
 	select MAINBOARD_HAS_TPM1
 	select DRIVERS_LENOVO_HYBRID_GRAPHICS
+	select MAINBOARD_HAS_LIBGFXINIT
+	select GFX_GMA_INTERNAL_IS_LVDS
+
 	# Workaround for EC/KBC IRQ1.
 	select SERIRQ_CONTINUOUS_MODE
 
+if BOARD_LENOVO_BASEBOARD_T530
+
 config HAVE_IFD_BIN
 	bool
 	default n
@@ -32,13 +35,24 @@
 	bool
 	default n
 
+config VARIANT_DIR
+	string
+	default "t530" if BOARD_LENOVO_T530
+	default "w530" if BOARD_LENOVO_W530
+
 config MAINBOARD_DIR
 	string
 	default lenovo/t530
 
+config DEVICETREE
+	string
+	default "variants/t530/devicetree.cb" if BOARD_LENOVO_T530
+	default "variants/w530/devicetree.cb" if BOARD_LENOVO_W530
+
 config MAINBOARD_PART_NUMBER
 	string
-	default "ThinkPad T530"
+	default "ThinkPad T530" if BOARD_LENOVO_T530
+	default "ThinkPad W530" if BOARD_LENOVO_W530
 
 config MAX_CPUS
 	int
@@ -54,7 +68,8 @@
 
 config VGA_BIOS_FILE
 	string
-	default "pci8086,0106.rom"
+	default "pci8086,0106.rom" if BOARD_LENOVO_T530
+	default "pci8086,0166.rom" if BOARD_LENOVO_W530
 
 config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
 	hex
@@ -68,4 +83,4 @@
 	bool
 	default y
 
-endif # BOARD_LENOVO_T530
+endif
diff --git a/src/mainboard/lenovo/t530/Kconfig.name b/src/mainboard/lenovo/t530/Kconfig.name
index b5dee66..9bcd2c5 100644
--- a/src/mainboard/lenovo/t530/Kconfig.name
+++ b/src/mainboard/lenovo/t530/Kconfig.name
@@ -1,2 +1,7 @@
 config BOARD_LENOVO_T530
-	bool "ThinkPad T530"
+		bool "ThinkPad T530"
+		select BOARD_LENOVO_BASEBOARD_T530
+
+config BOARD_LENOVO_W530
+		bool "ThinkPad W530"
+		select BOARD_LENOVO_BASEBOARD_T530
diff --git a/src/mainboard/lenovo/t530/Makefile.inc b/src/mainboard/lenovo/t530/Makefile.inc
index 9eb141a..7187013 100644
--- a/src/mainboard/lenovo/t530/Makefile.inc
+++ b/src/mainboard/lenovo/t530/Makefile.inc
@@ -14,4 +14,6 @@
 ##
 
 smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/t530/board_info.txt b/src/mainboard/lenovo/t530/board_info.txt
index 09ddde1..a659fe0 100644
--- a/src/mainboard/lenovo/t530/board_info.txt
+++ b/src/mainboard/lenovo/t530/board_info.txt
@@ -1,3 +1,5 @@
+Vendor name: Lenovo
+Board name: ThinkPad T530 baseboard
 Category: laptop
 ROM package: SOIC-8
 ROM protocol: SPI
diff --git a/src/mainboard/lenovo/t530/gma-mainboard.ads b/src/mainboard/lenovo/t530/gma-mainboard.ads
new file mode 100644
index 0000000..736dce71
--- /dev/null
+++ b/src/mainboard/lenovo/t530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      Internal,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c
index d2f7390..7470acc 100644
--- a/src/mainboard/lenovo/t530/romstage.c
+++ b/src/mainboard/lenovo/t530/romstage.c
@@ -22,7 +22,6 @@
 #include <console/console.h>
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/common/rcba.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
 #include <device/device.h>
@@ -70,28 +69,6 @@
 	RCBA32(BUC) = 0;
 }
 
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 1,  0 }, /* P0: USB double port upper, USB3, OC 0 */
-	{ 1, 1,  1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
-	{ 1, 2,  3 }, /* P2: Dock, USB3, OC 3 */
-	{ 1, 1, -1 }, /* P3: WWAN slot, no OC */
-	{ 1, 1,  2 }, /* P4: yellow USB, OC 2 */
-	{ 1, 0, -1 }, /* P5: ExpressCard slot, no OC */
-	{ 0, 0, -1 }, /* P6: color sensor(w530), no OC */
-	{ 1, 2, -1 }, /* P7: docking, no OC */
-	{ 1, 0, -1 }, /* P8: smart card reader, no OC */
-	{ 1, 1,  5 }, /* P9: USB port single (EHCI debug), OC 5 */
-	{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
-	{ 1, 0, -1 }, /* P11: bluetooth, no OC. */
-	{ 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/
-	{ 1, 1, -1 }, /* P13: camera, no OC */
-};
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only) {
-	read_spd (&spd[0], 0x50, id_only);
-	read_spd (&spd[2], 0x51, id_only);
-}
-
 void mainboard_early_init(int s3resume)
 {
 	hybrid_graphics_init();
diff --git a/src/mainboard/lenovo/t530/variants/t530/board_info.txt b/src/mainboard/lenovo/t530/variants/t530/board_info.txt
new file mode 100644
index 0000000..49f09e5
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/t530/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Lenovo
+Board name: ThinkPad T530
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/lenovo/t530/data.vbt b/src/mainboard/lenovo/t530/variants/t530/data.vbt
similarity index 100%
rename from src/mainboard/lenovo/t530/data.vbt
rename to src/mainboard/lenovo/t530/variants/t530/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/variants/t530/devicetree.cb
similarity index 100%
rename from src/mainboard/lenovo/t530/devicetree.cb
rename to src/mainboard/lenovo/t530/variants/t530/devicetree.cb
diff --git a/src/mainboard/lenovo/t530/gpio.c b/src/mainboard/lenovo/t530/variants/t530/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/t530/gpio.c
rename to src/mainboard/lenovo/t530/variants/t530/gpio.c
diff --git a/src/mainboard/lenovo/t530/variants/t530/romstage.c b/src/mainboard/lenovo/t530/variants/t530/romstage.c
new file mode 100644
index 0000000..7138de2
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/t530/romstage.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x51, id_only);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1,  0 }, /* P0: USB double port upper, USB3, OC 0 */
+	{ 1, 1,  1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
+	{ 1, 2,  3 }, /* P2: Dock, USB3, OC 3 */
+	{ 1, 1, -1 }, /* P3: WWAN slot, no OC */
+	{ 1, 1,  2 }, /* P4: yellow USB, OC 2 */
+	{ 1, 0, -1 }, /* P5: ExpressCard slot, no OC */
+	{ 0, 0, -1 }, /* P6: empty */
+	{ 1, 2, -1 }, /* P7: docking, no OC */
+	{ 1, 0, -1 }, /* P8: smart card reader, no OC */
+	{ 1, 1,  5 }, /* P9: USB port single (EHCI debug), OC 5 */
+	{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
+	{ 1, 0, -1 }, /* P11: bluetooth, no OC. */
+	{ 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/
+	{ 1, 1, -1 }, /* P13: camera, no OC */
+};
diff --git a/src/mainboard/lenovo/t530/variants/w530/board_info.txt b/src/mainboard/lenovo/t530/variants/w530/board_info.txt
new file mode 100644
index 0000000..d7d3679
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Lenovo
+Board name: ThinkPad W530
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: n
+Release year: 2012
diff --git a/src/mainboard/lenovo/t530/variants/w530/data.vbt b/src/mainboard/lenovo/t530/variants/w530/data.vbt
new file mode 100644
index 0000000..4db2694
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/t530/variants/w530/devicetree.cb b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb
new file mode 100644
index 0000000..2a22d4e
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/devicetree.cb
@@ -0,0 +1,224 @@
+chip northbridge/intel/sandybridge
+	# IGD Displays
+	register "gfx.ndid" = "3"
+	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"
+
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	register "gpu_dp_b_hotplug" = "0"
+	register "gpu_dp_c_hotplug" = "0"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"                  # LVDS
+	register "gpu_panel_power_cycle_delay" = "6"            # T7: 500ms
+	register "gpu_panel_power_up_delay" = "100"             # T1+T2: 10ms
+	register "gpu_panel_power_down_delay" = "100"           # T5+T6: 10ms
+	register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
+	register "gpu_panel_power_backlight_on_delay" = "2000"  # T3: 200ms
+	register "gfx.use_spread_spectrum_clock" = "1"
+	register "gfx.link_frequency_270_mhz" = "1"
+	register "gpu_cpu_backlight" = "0x1155"
+	register "gpu_pch_backlight" = "0x11551155"
+
+	device cpu_cluster 0x0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0x0 on
+			end
+		end
+		chip cpu/intel/model_206ax # FIXME: check all registers
+			register "c1_acpower" = "1"
+			register "c1_battery" = "1"
+			register "c2_acpower" = "3"
+			register "c2_battery" = "3"
+			register "c3_acpower" = "5"
+			register "c3_battery" = "5"
+			device lapic 0xacac off
+			end
+		end
+	end
+
+	register "pci_mmio_size" = "2048"
+
+	device domain 0x0 on
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "alt_gp_smi_en" = "0x0000"
+			register "gpi1_routing" = "2"
+			register "gpi13_routing" = "2"
+
+			register "c2_latency" = "0x0065"
+			register "docking_supported" = "1"
+			register "gen1_dec" = "0x007c1601"
+			register "gen2_dec" = "0x000c15e1"
+			register "gen4_dec" = "0x000c06a1"
+			register "p_cnt_throttling_supported" = "1"
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+			register "pcie_port_coalesce" = "1"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "spi_uvscc" = "0x2005"
+			register "spi_lvscc" = "0x2005"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x04000201"
+			register "xhci_switchable_ports" = "0x0000000f"
+			device pci 14.0 on # USB 3.0 Controller
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 16.0 on # Management Engine Interface 1
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 16.1 off # Management Engine Interface 2
+			end
+			device pci 16.2 off # Management Engine IDE-R
+			end
+			device pci 16.3 on # Management Engine KT
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 19.0 on # Intel Gigabit Ethernet
+				subsystemid 0x17aa 0x21f3
+			end
+			device pci 1a.0 on # USB2 EHCI #2
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1b.0 on # High Definition Audio Audio controller
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1c.0 on # PCIe Port #1
+				subsystemid 0x17aa 0x21f6
+				chip drivers/ricoh/rce822 # Ricoh cardreader
+					register "disable_mask" = "0x83"
+					register "sdwppol" = "1"
+					device pci 00.0 on # Ricoh SD card reader
+						subsystemid 0x17aa 0x21f6
+					end
+				end
+			end
+			device pci 1c.1 on # PCIe Port #2
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1c.2 on # PCIe Port #3
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1c.3 off # PCIe Port #4
+			end
+			device pci 1c.4 off # PCIe Port #5
+			end
+			device pci 1c.5 off # PCIe Port #6
+			end
+			device pci 1c.6 off # PCIe Port #7
+			end
+			device pci 1c.7 off # PCIe Port #8
+			end
+			device pci 1d.0 on # USB2 EHCI #1
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1e.0 off # PCI bridge
+			end
+			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+				subsystemid 0x17aa 0x21f6
+				chip ec/lenovo/pmh7
+					register "backlight_enable" = "0x01"
+					register "dock_event_enable" = "0x01"
+					device pnp ff.1 on # dummy
+					end
+				end
+
+				chip drivers/pc80/tpm
+					device pnp 0c31.0 on end
+				end
+
+				chip ec/lenovo/h8
+					register "beepmask0" = "0x00"
+					register "beepmask1" = "0x86"
+
+					register "config0" = "0xa7"
+					register "config1" = "0x01"
+					register "config2" = "0xa0"
+					register "config3" = "0xe2"
+
+					register "event2_enable" = "0xff"
+					register "event3_enable" = "0xff"
+					register "event4_enable" = "0xd0"
+					register "event5_enable" = "0xfc"
+					register "event6_enable" = "0x00"
+					register "event7_enable" = "0x01"
+					register "event8_enable" = "0x7b"
+					register "event9_enable" = "0xff"
+					register "eventa_enable" = "0x01"
+					register "eventb_enable" = "0x00"
+					register "eventc_enable" = "0xff"
+					register "eventd_enable" = "0xff"
+					register "evente_enable" = "0x0d"
+
+					register "has_keyboard_backlight" = "1"
+					register "has_power_management_beeps" = "0"
+					register "has_bdc_detection" = "1"
+					register "bdc_gpio_num" = "54"
+					register "bdc_gpio_lvl" = "0"
+
+					device pnp ff.2 on # dummy
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						io 0x64 = 0x1600
+						io 0x66 = 0x1604
+					end
+				end
+				chip drivers/lenovo/hybrid_graphics
+					device pnp ff.f on end # dummy
+
+					register "detect_gpio" = "21"
+
+					register "has_panel_hybrid_gpio" = "1"
+					register "panel_hybrid_gpio" = "52"
+					register "panel_integrated_lvl" = "1"
+
+					register "has_backlight_gpio" = "0"
+					register "has_dgpu_power_gpio" = "0"
+
+					register "has_thinker1" = "0"
+				end
+			end
+			device pci 1f.2 on # SATA Controller 1
+				subsystemid 0x17aa 0x21f6
+			end
+			device pci 1f.3 on # SMBus
+				subsystemid 0x17aa 0x21f6
+				chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip
+					device i2c 54 on
+					end
+					device i2c 55 on
+					end
+					device i2c 56 on
+					end
+					device i2c 57 on
+					end
+					device i2c 5c on
+					end
+					device i2c 5d on
+					end
+					device i2c 5e on
+					end
+					device i2c 5f on
+					end
+				end
+			end
+			device pci 1f.5 off # SATA Controller 2
+			end
+			device pci 1f.6 off # Thermal
+			end
+		end
+		device pci 00.0 on # Host bridge Host bridge
+			subsystemid 0x17aa 0x21f6
+		end
+		device pci 01.0 on # PCIe Bridge for discrete graphics
+			subsystemid 0x17aa 0x21f6
+		end
+		device pci 02.0 on # Internal graphics VGA controller
+			subsystemid 0x17aa 0x21f5
+		end
+	end
+end
diff --git a/src/mainboard/lenovo/t530/variants/w530/gpio.c b/src/mainboard/lenovo/t530/variants/w530/gpio.c
new file mode 100644
index 0000000..c6a10d1
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/gpio.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_GPIO,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_GPIO,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio5 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_OUTPUT,
+	.gpio10 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio8 = GPIO_LEVEL_LOW,
+	.gpio10 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio24 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio1 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_GPIO,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_OUTPUT,
+	.gpio53 = GPIO_DIR_OUTPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio33 = GPIO_LEVEL_HIGH,
+	.gpio43 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_HIGH,
+	.gpio52 = GPIO_LEVEL_HIGH,
+	.gpio53 = GPIO_LEVEL_HIGH,
+	.gpio55 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_GPIO,
+	.gpio65 = GPIO_MODE_GPIO,
+	.gpio66 = GPIO_MODE_GPIO,
+	.gpio67 = GPIO_MODE_GPIO,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/lenovo/t530/variants/w530/romstage.c b/src/mainboard/lenovo/t530/variants/w530/romstage.c
new file mode 100644
index 0000000..9fe6f84
--- /dev/null
+++ b/src/mainboard/lenovo/t530/variants/w530/romstage.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[1], 0x52, id_only);
+	read_spd(&spd[2], 0x51, id_only);
+	read_spd(&spd[3], 0x53, id_only);
+}
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1,  0 }, /* P0: USB double port upper, USB3, OC 0 */
+	{ 1, 1,  1 }, /* P1: USB double port lower, USB3, (EHCI debug) OC 1 */
+	{ 1, 2,  3 }, /* P2: Dock, USB3, OC 3 */
+	{ 1, 1, -1 }, /* P3: WWAN slot, no OC */
+	{ 1, 1,  2 }, /* P4: yellow USB, OC 2 */
+	{ 1, 0, -1 }, /* P5: ExpressCard slot, no OC */
+	{ 1, 0, -1 }, /* P6: color sensor, no OC */
+	{ 1, 2, -1 }, /* P7: docking, no OC */
+	{ 1, 0, -1 }, /* P8: smart card reader, no OC */
+	{ 1, 1,  5 }, /* P9: USB port single (EHCI debug), OC 5 */
+	{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
+	{ 1, 0, -1 }, /* P11: bluetooth, no OC. */
+	{ 1, 3, -1 }, /* P12: wlan, no OC - disabled in vendor bios*/
+	{ 1, 1, -1 }, /* P13: camera, no OC */
+};