commit | 9234d9231b177c80281805301d4c67c8ca4d02bb | [log] [tgz] |
---|---|---|
author | Tim Wawrzynczak <twawrzynczak@chromium.org> | Wed Nov 24 09:19:56 2021 -0700 |
committer | Felix Held <felix-coreboot@felixheld.de> | Fri Nov 26 11:19:52 2021 +0000 |
tree | 797e9b771e74e039ca0c9da504099e8851d3dd28 | |
parent | 40713aaa4347ba0b3fac591b8f1f5b437c6b2ca4 [diff] |
ec/google/chromeec: Support 5 temperature sensors Some boards with the chrome EC will need to support more than 4 temperature sensors, so modify the number of TSRs supported when generating the ACPI code. Note that the EC memory map already has support for up to 16 TSRs, so no change is required on the EC side. BUG=b:207585491 TEST=with previous patch and some test data in brya0 overridetree.cb, dump the SSDT and verify that all of the existing Methods for TSR0-TSR3 are also added for TSR4, as well as all Notify, etc. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.