soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKE

Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1]

switched CNL-based mainboards from using FSP for HECI disablement to SBI
msg, but this causes google/hatch to hang when attempting to unhide p2sb
as part of disabling HECI1 via SBI during SMM, so switch to using
PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not
support PMC disablement method, so they remain using SBI.

Test: build/boot google/hatch, verify HECI1 disabled via console log and
lspci in booted OS.

Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f85cd15..94f0b48 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -5,15 +5,17 @@
 	bool
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
-	select HAVE_INTEL_FSP_REPO
-	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 	select HAVE_EXP_X86_64_SUPPORT
+	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
+	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 
 config SOC_INTEL_WHISKEYLAKE
 	bool
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
 	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
 	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 
 config SOC_INTEL_COMETLAKE
@@ -21,7 +23,9 @@
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
 	select HAVE_INTEL_FSP_REPO
+	select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
 	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
 
 config SOC_INTEL_COMETLAKE_1
 	bool
@@ -109,7 +113,6 @@
 
 config DISABLE_HECI1_AT_PRE_BOOT
 	default y if MAINBOARD_HAS_CHROMEOS
-	select HECI_DISABLE_USING_SMM
 
 config MAX_CPUS
 	int