commit 575a2e589d50018946c6e7511cfc98610ea5bac8
author Matt DeVillier <matt.devillier@gmail.com> Thu Feb 10 17:01:35 2022 -0600
committer Felix Held <felix-coreboot@felixheld.de> Tue Feb 15 18:10:59 2022 +0000
tree 2feffce59cfc77f02633fa5280b863768944cb24
parent 148b5456715cc8eebd25878c67ce906b6fc3adce

soc/intel/cnl: switch to PMC/IPC for HECI disable on SOC_INTEL_COMETLAKE

Commit d6dbd933 [soc/intel/cannonlake: Use SBI msg to disable HECI1]

switched CNL-based mainboards from using FSP for HECI disablement to SBI
msg, but this causes google/hatch to hang when attempting to unhide p2sb
as part of disabling HECI1 via SBI during SMM, so switch to using
PMC/IPC method. SOC_INTEL_WHISKEYLAKE and SOC_INTEL_COFFEELAKE do not
support PMC disablement method, so they remain using SBI.

Test: build/boot google/hatch, verify HECI1 disabled via console log and
lspci in booted OS.

Change-Id: I06f0eb312b579af4a0fe826403374dcd99689d21
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/soc/intel/cannonlake/Kconfig

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index f85cd15..94f0b48 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -5,15 +5,17 @@
 	bool
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
-	select HAVE_INTEL_FSP_REPO
-	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 	select HAVE_EXP_X86_64_SUPPORT
+	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
+	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 
 config SOC_INTEL_WHISKEYLAKE
 	bool
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
 	select HAVE_INTEL_FSP_REPO
+	select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
 	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
 
 config SOC_INTEL_COMETLAKE
@@ -21,7 +23,9 @@
 	select SOC_INTEL_CANNONLAKE_BASE
 	select FSP_USES_CB_STACK
 	select HAVE_INTEL_FSP_REPO
+	select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
 	select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
+	select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
 
 config SOC_INTEL_COMETLAKE_1
 	bool
@@ -109,7 +113,6 @@
 
 config DISABLE_HECI1_AT_PRE_BOOT
 	default y if MAINBOARD_HAS_CHROMEOS
-	select HECI_DISABLE_USING_SMM
 
 config MAX_CPUS
 	int

src/soc/intel/cannonlake/finalize.c

diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c
index 63749f9..5410377 100644
--- a/src/soc/intel/cannonlake/finalize.c
+++ b/src/soc/intel/cannonlake/finalize.c
@@ -7,6 +7,7 @@
 #include <device/mmio.h>
 #include <device/pci.h>
 #include <intelblocks/cpulib.h>
+#include <intelblocks/cse.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <intelblocks/pmclib.h>
@@ -95,6 +96,9 @@
 	pch_finalize();
 	apm_control(APM_CNT_FINALIZE);
 	sa_finalize();
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) &&
+			CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC))
+		heci1_disable();
 
 	/* Indicate finalize step with post code */
 	post_code(POST_OS_BOOT);

src/soc/intel/cannonlake/smihandler.c

diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index 88b58e8..ac25990 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -16,7 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
+	if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
 		heci1_disable();
 }