soc/intel/common: Adapt XHCI elog driver for reuse
Currently this XHCI driver assumes the PCH XHCI controller, but the TCSS
or North XHCI block has a similar enough PCI MMIO structure to make this
code mostly reusable.
1) Rename everything to drop the `pch_` prefix
2) xhci_update_wake_event() now takes in a pci_devfn_t for the XHCI
controller
3) soc_get_xhci_usb_info() also now takes a pci_devfn_t for the XHCI
controller
BUG=b:172279037
TEST=plug in USB keyboard while in S0, enter S0ix and verify entry via
EC; type on keyboard, verify it wakes up, eventlog contains:
39 | 2020-12-10 09:40:21 | S0ix Enter
40 | 2020-12-10 09:40:42 | S0ix Exit
41 | 2020-12-10 09:40:42 | Wake Source | PME - XHCI (USB 2.0 port) | 1
42 | 2020-12-10 09:40:42 | Wake Source | GPE # | 109
which verifies it still functions for the PCH XHCI controller
Change-Id: I9f28354e031e3eda587f4faf8ef7595dce8b33ea
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47411
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/xhci/elog.c b/src/soc/intel/common/block/xhci/elog.c
index c3043cb..fb59897 100644
--- a/src/soc/intel/common/block/xhci/elog.c
+++ b/src/soc/intel/common/block/xhci/elog.c
@@ -20,23 +20,23 @@
#define XHCI_STATUS_PLS_MASK (0xF << XHCI_STATUS_PLS_SHIFT)
#define XHCI_STATUS_PLS_RESUME (15 << XHCI_STATUS_PLS_SHIFT)
-static bool pch_xhci_csc_set(uint32_t port_status)
+static bool xhci_csc_set(uint32_t port_status)
{
return !!(port_status & XHCI_STATUS_CSC);
}
-static bool pch_xhci_wake_capable(uint32_t port_status)
+static bool xhci_wake_capable(uint32_t port_status)
{
return !!((port_status & XHCI_STATUS_WCE) |
(port_status & XHCI_STATUS_WDE));
}
-static bool pch_xhci_plc_set(uint32_t port_status)
+static bool xhci_plc_set(uint32_t port_status)
{
return !!(port_status & XHCI_STATUS_PLC);
}
-static bool pch_xhci_resume(uint32_t port_status)
+static bool xhci_resume(uint32_t port_status)
{
return (port_status & XHCI_STATUS_PLS_MASK) == XHCI_STATUS_PLS_RESUME;
}
@@ -55,7 +55,7 @@
* true : Wake source was found.
* false : Wake source was not found.
*/
-static bool pch_xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t event)
+static bool xhci_port_wake_check(uintptr_t base, uint8_t num, uint8_t host_event, uint8_t event)
{
uint32_t i, port_status;
bool found = false;
@@ -73,8 +73,9 @@
* connect/disconnect to identify if the port caused wake
* event for USB attach/detach.
*/
- if (pch_xhci_csc_set(port_status) &&
- pch_xhci_wake_capable(port_status)) {
+ if (xhci_csc_set(port_status) &&
+ xhci_wake_capable(port_status)) {
+ elog_add_event_wake(host_event, 0);
elog_add_event_wake(event, i + 1);
found = true;
continue;
@@ -84,8 +85,9 @@
* Check if PLC is set and PLS indicates resume to identify if
* the port caused wake event for USB activity.
*/
- if (pch_xhci_plc_set(port_status) &&
- pch_xhci_resume(port_status)) {
+ if (xhci_plc_set(port_status) &&
+ xhci_resume(port_status)) {
+ elog_add_event_wake(host_event, 0);
elog_add_event_wake(event, i + 1);
found = true;
}
@@ -93,50 +95,35 @@
return found;
}
-/*
- * Update elog event and instance depending upon the USB2 port that caused
- * the wake event.
- *
- * Return value:
- * true = Indicates that USB2 wake event was found.
- * false = Indicates that USB2 wake event was not found.
- */
-static inline bool pch_xhci_usb2_update_wake_event(uintptr_t mmio_base,
- const struct xhci_usb_info *info)
+bool xhci_update_wake_event(const struct xhci_wake_info *wake_info,
+ size_t wake_info_count)
{
- return pch_xhci_port_wake_check(mmio_base + info->usb2_port_status_reg,
- info->num_usb2_ports,
- ELOG_WAKE_SOURCE_PME_XHCI_USB_2);
-}
-
-/*
- * Update elog event and instance depending upon the USB3 port that caused
- * the wake event.
- *
- * Return value:
- * true = Indicates that USB3 wake event was found.
- * false = Indicates that USB3 wake event was not found.
- */
-static inline bool pch_xhci_usb3_update_wake_event(uintptr_t mmio_base,
- const struct xhci_usb_info *info)
-{
- return pch_xhci_port_wake_check(mmio_base + info->usb3_port_status_reg,
- info->num_usb3_ports,
- ELOG_WAKE_SOURCE_PME_XHCI_USB_3);
-}
-
-bool pch_xhci_update_wake_event(const struct xhci_usb_info *info)
-{
+ const struct xhci_usb_info *usb_info;
uintptr_t mmio_base;
bool event_found = false;
- mmio_base = ALIGN_DOWN(pci_read_config32(PCH_DEV_XHCI,
- PCI_BASE_ADDRESS_0), 16);
+ size_t i;
- if (pch_xhci_usb2_update_wake_event(mmio_base, info))
- event_found = true;
+ for (i = 0; i < wake_info_count; ++i) {
+ /* Assumes BAR0 is MBAR */
+ mmio_base = pci_s_read_config32(wake_info[i].xhci_dev,
+ PCI_BASE_ADDRESS_0);
+ mmio_base &= ~PCI_BASE_ADDRESS_MEM_ATTR_MASK;
+ usb_info = soc_get_xhci_usb_info(wake_info[i].xhci_dev);
- if (pch_xhci_usb3_update_wake_event(mmio_base, info))
- event_found = true;
+ /* Check USB2 port status & control registers */
+ if (xhci_port_wake_check(mmio_base + usb_info->usb2_port_status_reg,
+ usb_info->num_usb2_ports,
+ wake_info[i].elog_wake_type_host,
+ ELOG_WAKE_SOURCE_PME_XHCI_USB_2))
+ event_found = true;
+
+ /* Check USB3 port status & control registers */
+ if (xhci_port_wake_check(mmio_base + usb_info->usb3_port_status_reg,
+ usb_info->num_usb3_ports,
+ wake_info[i].elog_wake_type_host,
+ ELOG_WAKE_SOURCE_PME_XHCI_USB_3))
+ event_found = true;
+ }
return event_found;
}
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
index 47f2567..705fbb0 100644
--- a/src/soc/intel/common/block/xhci/xhci.c
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -57,7 +57,7 @@
unsigned int port_id))
{
struct device *xhci, *hub = NULL, *port = NULL;
- const struct xhci_usb_info *info = soc_get_xhci_usb_info();
+ const struct xhci_usb_info *info = soc_get_xhci_usb_info(PCH_DEVFN_XHCI);
struct drivers_usb_acpi_config *config;
bool enable;