tree d521bb47a06e2d46c49af23a22b01c75064eb46f
parent 16c762607794b618ed89eeeab025e1f9e3b2a848
author Michał Żygowski <michal.zygowski@3mdeb.com> 1669211297 +0100
committer Felix Held <felix-coreboot@felixheld.de> 1681230906 +0000

soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden

Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>