commit 56352e1f8055c3495c71e1856f0d26923be44ed0
author Mario Scheithauer <mario.scheithauer@siemens.com> Thu Jul 11 14:31:34 2019 +0200
committer Martin Roth <martinroth@google.com> Fri Jul 12 17:09:21 2019 +0000
tree 89c017af6cf28989a4d4c9fd40fd53e6ea5a22cf
parent b14f3b8b0b005a5de8f5bcbb84d44fce9d0bc6b8

mb/siemens/mc_apl3: Enable LPSS UART 1

By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.

Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
index 9159ba1..e0fec7c 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/gpio.c
@@ -325,8 +325,9 @@
 	PAD_CFG_GPI(GPIO_39, DN_20K, DEEP),	/* LPSS_UART0_TXD - unused */
 	PAD_CFG_GPI(GPIO_40, DN_20K, DEEP),	/* LPSS_UART0_RTS - unused */
 	PAD_CFG_GPI(GPIO_41, UP_20K, DEEP),	/* LPSS_UART0_CTS - unused */
-	PAD_CFG_GPI(GPIO_42, UP_20K, DEEP),	/* LPSS_UART1_RXD - unused */
-	PAD_CFG_GPI(GPIO_43, DN_20K, DEEP),	/* LPSS_UART1_TXD - unused */
+	PAD_CFG_NF(GPIO_42, UP_20K, DEEP, NF1), /* LPSS_UART1_RXD */
+	/* LPSS_UART1_TXD */
+	PAD_CFG_NF_IOSSTATE(GPIO_43, NATIVE, DEEP, NF1, Tx1RxDCRx0),
 	PAD_CFG_GPI(GPIO_44, UP_20K, DEEP),	/* LPSS_UART1_RTS - unused */
 	PAD_CFG_GPI(GPIO_45, UP_20K, DEEP),	/* LPSS_UART1_CTS - unused */
 	PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1),	/* LPSS_UART2_RXD */