soc/mediatek/mt8195: add eDP support
BUG=b:189985956
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I37326ad053295aa4944c8291e4e7a7d69c8f3f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55573
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc
index e75455f..181e99c 100644
--- a/src/soc/mediatek/mt8195/Makefile.inc
+++ b/src/soc/mediatek/mt8195/Makefile.inc
@@ -49,6 +49,7 @@
ramstage-y += ../common/auxadc.c
ramstage-y += ../common/ddp.c ddp.c
+ramstage-y += dp_intf.c dptx.c dptx_hal.c
ramstage-y += emi.c
ramstage-y += ../common/flash_controller.c
ramstage-y += ../common/gpio.c gpio.c
diff --git a/src/soc/mediatek/mt8195/dp_intf.c b/src/soc/mediatek/mt8195/dp_intf.c
new file mode 100644
index 0000000..6683767
--- /dev/null
+++ b/src/soc/mediatek/mt8195/dp_intf.c
@@ -0,0 +1,309 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/dp_intf.h>
+#include <soc/mcucfg.h>
+#include <soc/pll.h>
+#include <soc/pll_common.h>
+#include <soc/spm.h>
+#include <string.h>
+#include <timer.h>
+
+static void mtk_dpintf_mask(struct mtk_dpintf *dpintf, u32 offset, u32 val, u32 mask)
+{
+ clrsetbits32(dpintf->regs + offset, mask, val);
+}
+
+static void mtk_dpintf_sw_reset(struct mtk_dpintf *dpintf, bool reset)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_RET, reset ? RST : 0, RST);
+}
+
+static void mtk_dpintf_enable(struct mtk_dpintf *dpintf)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_EN, EN, EN);
+}
+
+static void mtk_dpintf_config_hsync(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_TGEN_HWIDTH,
+ sync->sync_width << HPW, HPW_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_TGEN_HPORCH,
+ sync->back_porch << HBP, HBP_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_TGEN_HPORCH,
+ sync->front_porch << HFP, HFP_MASK);
+}
+
+static void mtk_dpintf_config_vsync(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync,
+ u32 width_addr, u32 porch_addr)
+{
+ mtk_dpintf_mask(dpintf, width_addr,
+ sync->sync_width << VSYNC_WIDTH_SHIFT,
+ VSYNC_WIDTH_MASK);
+ mtk_dpintf_mask(dpintf, width_addr,
+ sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
+ VSYNC_HALF_LINE_MASK);
+ mtk_dpintf_mask(dpintf, porch_addr,
+ sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
+ VSYNC_BACK_PORCH_MASK);
+ mtk_dpintf_mask(dpintf, porch_addr,
+ sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
+ VSYNC_FRONT_PORCH_MASK);
+}
+
+static void mtk_dpintf_config_vsync_lodd(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync)
+{
+ mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH,
+ DPINTF_TGEN_VPORCH);
+}
+
+static void mtk_dpintf_config_vsync_leven(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync)
+{
+ mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_LEVEN,
+ DPINTF_TGEN_VPORCH_LEVEN);
+}
+
+static void mtk_dpintf_config_vsync_rodd(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync)
+{
+ mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_RODD,
+ DPINTF_TGEN_VPORCH_RODD);
+}
+
+static void mtk_dpintf_config_vsync_reven(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_sync_param *sync)
+{
+ mtk_dpintf_config_vsync(dpintf, sync, DPINTF_TGEN_VWIDTH_REVEN,
+ DPINTF_TGEN_VPORCH_REVEN);
+}
+
+static void mtk_dpintf_config_pol(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_polarities *dpintf_pol)
+{
+ u32 pol;
+
+ pol = (dpintf_pol->hsync_pol == MTK_DPINTF_POLARITY_RISING ? 0 : HSYNC_POL) |
+ (dpintf_pol->vsync_pol == MTK_DPINTF_POLARITY_RISING ? 0 : VSYNC_POL);
+ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, pol, HSYNC_POL | VSYNC_POL);
+}
+
+static void mtk_dpintf_config_3d(struct mtk_dpintf *dpintf, bool en_3d)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
+}
+
+static void mtk_dpintf_config_interface(struct mtk_dpintf *dpintf, bool inter)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_CON, inter ? INTL_EN : 0, INTL_EN);
+}
+
+static void mtk_dpintf_config_fb_size(struct mtk_dpintf *dpintf,
+ u32 width, u32 height)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_SIZE, width << HSIZE, HSIZE_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_SIZE, height << VSIZE, VSIZE_MASK);
+}
+
+static void mtk_dpintf_config_channel_limit(struct mtk_dpintf *dpintf,
+ struct mtk_dpintf_yc_limit *limit)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_Y_LIMIT,
+ limit->y_bottom << Y_LIMINT_BOT, Y_LIMINT_BOT_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_Y_LIMIT,
+ limit->y_top << Y_LIMINT_TOP, Y_LIMINT_TOP_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_C_LIMIT,
+ limit->c_bottom << C_LIMIT_BOT, C_LIMIT_BOT_MASK);
+ mtk_dpintf_mask(dpintf, DPINTF_C_LIMIT,
+ limit->c_top << C_LIMIT_TOP, C_LIMIT_TOP_MASK);
+}
+
+static void mtk_dpintf_config_bit_num(struct mtk_dpintf *dpintf,
+ enum mtk_dpintf_out_bit_num num)
+{
+ u32 val;
+
+ switch (num) {
+ case MTK_DPINTF_OUT_BIT_NUM_8BITS:
+ val = OUT_BIT_8;
+ break;
+ case MTK_DPINTF_OUT_BIT_NUM_10BITS:
+ val = OUT_BIT_10;
+ break;
+ case MTK_DPINTF_OUT_BIT_NUM_12BITS:
+ val = OUT_BIT_12;
+ break;
+ case MTK_DPINTF_OUT_BIT_NUM_16BITS:
+ val = OUT_BIT_16;
+ break;
+ default:
+ val = OUT_BIT_8;
+ break;
+ }
+ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, OUT_BIT_MASK);
+}
+
+static void mtk_dpintf_config_channel_swap(struct mtk_dpintf *dpintf,
+ enum mtk_dpintf_out_channel_swap swap)
+{
+ u32 val;
+
+ switch (swap) {
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_RGB:
+ val = SWAP_RGB;
+ break;
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_GBR:
+ val = SWAP_GBR;
+ break;
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_BRG:
+ val = SWAP_BRG;
+ break;
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_RBG:
+ val = SWAP_RBG;
+ break;
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_GRB:
+ val = SWAP_GRB;
+ break;
+ case MTK_DPINTF_OUT_CHANNEL_SWAP_BGR:
+ val = SWAP_BGR;
+ break;
+ default:
+ val = SWAP_RGB;
+ break;
+ }
+
+ mtk_dpintf_mask(dpintf, DPINTF_OUTPUT_SETTING, val, CH_SWAP_MASK);
+}
+
+static void mtk_dpintf_config_yuv422_enable(struct mtk_dpintf *dpintf, bool enable)
+{
+ mtk_dpintf_mask(dpintf, DPINTF_CON, enable ? YUV422_EN : 0, YUV422_EN);
+}
+
+static void mtk_dpintf_config_color_format(struct mtk_dpintf *dpintf,
+ enum mtk_dpintf_out_color_format format)
+{
+ bool enable;
+ int channel_swap;
+
+ if (format == MTK_DPINTF_COLOR_FORMAT_YCBCR_444 ||
+ format == MTK_DPINTF_COLOR_FORMAT_YCBCR_444_FULL) {
+ enable = false;
+ channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_BGR;
+ } else if (format == MTK_DPINTF_COLOR_FORMAT_YCBCR_422 ||
+ format == MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL) {
+ enable = true;
+ channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB;
+ } else {
+ enable = false;
+ channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB;
+ }
+
+ mtk_dpintf_config_yuv422_enable(dpintf, enable);
+ mtk_dpintf_config_channel_swap(dpintf, channel_swap);
+}
+
+static int mtk_dpintf_power_on(struct mtk_dpintf *dpintf, const struct edid *edid)
+{
+ u32 clksrc;
+ u32 pll_rate;
+
+ if (edid->mode.pixel_clock < 70000)
+ clksrc = TVDPLL_D16;
+ else if (edid->mode.pixel_clock < 200000)
+ clksrc = TVDPLL_D8;
+ else
+ clksrc = TVDPLL_D4;
+
+ pll_rate = edid->mode.pixel_clock * 1000 * (1 << ((clksrc + 1) / 2));
+
+ mt_pll_set_tvd_pll1_freq(pll_rate / 4);
+ edp_mux_set_sel(clksrc);
+
+ mtk_dpintf_enable(dpintf);
+
+ return 0;
+}
+
+static int mtk_dpintf_set_display_mode(struct mtk_dpintf *dpintf,
+ const struct edid *edid)
+{
+ struct mtk_dpintf_yc_limit limit;
+ struct mtk_dpintf_polarities dpintf_pol;
+ struct mtk_dpintf_sync_param hsync;
+ struct mtk_dpintf_sync_param vsync_lodd = { 0 };
+ struct mtk_dpintf_sync_param vsync_leven = { 0 };
+ struct mtk_dpintf_sync_param vsync_rodd = { 0 };
+ struct mtk_dpintf_sync_param vsync_reven = { 0 };
+
+ vsync_lodd.back_porch = edid->mode.vbl - edid->mode.vso -
+ edid->mode.vspw - edid->mode.vborder;
+ vsync_lodd.front_porch = edid->mode.vso - edid->mode.vborder;
+ vsync_lodd.sync_width = edid->mode.vspw;
+ vsync_lodd.shift_half_line = false;
+
+ hsync.sync_width = edid->mode.hspw / 4;
+ hsync.back_porch = (edid->mode.hbl - edid->mode.hso -
+ edid->mode.hspw - edid->mode.hborder) / 4;
+ hsync.front_porch = (edid->mode.hso - edid->mode.hborder) / 4;
+ hsync.shift_half_line = false;
+
+ /* Let pll_rate be able to fix the valid range of tvdpll (1G~2GHz) */
+ limit.c_bottom = 0x0000;
+ limit.c_top = 0xfff;
+ limit.y_bottom = 0x0000;
+ limit.y_top = 0xfff;
+
+ dpintf_pol.ck_pol = MTK_DPINTF_POLARITY_FALLING;
+ dpintf_pol.de_pol = MTK_DPINTF_POLARITY_RISING;
+ dpintf_pol.hsync_pol = (edid->mode.phsync == '+') ?
+ MTK_DPINTF_POLARITY_FALLING :
+ MTK_DPINTF_POLARITY_RISING;
+ dpintf_pol.vsync_pol = (edid->mode.pvsync == '+') ?
+ MTK_DPINTF_POLARITY_FALLING :
+ MTK_DPINTF_POLARITY_RISING;
+
+ mtk_dpintf_sw_reset(dpintf, true);
+ mtk_dpintf_config_pol(dpintf, &dpintf_pol);
+
+ mtk_dpintf_config_hsync(dpintf, &hsync);
+ mtk_dpintf_config_vsync_lodd(dpintf, &vsync_lodd);
+ mtk_dpintf_config_vsync_rodd(dpintf, &vsync_rodd);
+ mtk_dpintf_config_vsync_leven(dpintf, &vsync_leven);
+ mtk_dpintf_config_vsync_reven(dpintf, &vsync_reven);
+
+ mtk_dpintf_config_3d(dpintf, false);
+ mtk_dpintf_config_interface(dpintf, false);
+ mtk_dpintf_config_fb_size(dpintf, edid->mode.ha, edid->mode.va);
+
+ mtk_dpintf_config_channel_limit(dpintf, &limit);
+ mtk_dpintf_config_bit_num(dpintf, dpintf->bit_num);
+ mtk_dpintf_config_channel_swap(dpintf, dpintf->channel_swap);
+ mtk_dpintf_config_color_format(dpintf, dpintf->color_format);
+
+ mtk_dpintf_mask(dpintf, DPINTF_CON, INPUT_2P_EN, INPUT_2P_EN);
+ mtk_dpintf_sw_reset(dpintf, false);
+
+ return 0;
+}
+
+void dp_intf_config(const struct edid *edid)
+{
+ struct mtk_dpintf dpintf = {
+ .regs = (void *)(DP_INTF0_BASE),
+ .color_format = MTK_DPINTF_COLOR_FORMAT_RGB,
+ .yc_map = MTK_DPINTF_OUT_YC_MAP_RGB,
+ .bit_num = MTK_DPINTF_OUT_BIT_NUM_8BITS,
+ .channel_swap = MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
+ };
+
+ mtk_dpintf_power_on(&dpintf, edid);
+ mtk_dpintf_set_display_mode(&dpintf, edid);
+}
diff --git a/src/soc/mediatek/mt8195/dptx.c b/src/soc/mediatek/mt8195/dptx.c
new file mode 100644
index 0000000..9ffad27
--- /dev/null
+++ b/src/soc/mediatek/mt8195/dptx.c
@@ -0,0 +1,1134 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <edid.h>
+#include <soc/addressmap.h>
+#include <soc/dptx.h>
+#include <soc/dptx_hal.h>
+#include <soc/dptx_reg.h>
+#include <soc/dp_intf.h>
+#include <string.h>
+#include <timer.h>
+
+#define ONE_BLOCK_SIZE 128
+
+#define DP_LINK_CONSTANT_N_VALUE 0x8000
+#define DP_LINK_STATUS_SIZE 6
+
+#define DP_LANE0_1_STATUS 0x202
+#define DP_LANE2_3_STATUS 0x203
+#define DP_LANE_CR_DONE (1 << 0)
+#define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
+#define DP_LANE_SYMBOL_LOCKED (1 << 2)
+
+#define DP_BRANCH_OUI_HEADER_SIZE 0xc
+#define DP_RECEIVER_CAP_SIZE 0xf
+#define DP_DSC_RECEIVER_CAP_SIZE 0xf
+#define EDP_PSR_RECEIVER_CAP_SIZE 2
+#define EDP_DISPLAY_CTL_CAP_SIZE 3
+#define DP_LTTPR_COMMON_CAP_SIZE 8
+#define DP_LTTPR_PHY_CAP_SIZE 3
+
+#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
+#define DP_TRAINING_AUX_RD_MASK 0x7f
+#define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)
+
+#define DP_EDP_DPCD_REV 0x700
+#define DP_EDP_11 0x00
+#define DP_EDP_12 0x01
+#define DP_EDP_13 0x02
+#define DP_EDP_14 0x03
+#define DP_EDP_14a 0x04
+#define DP_EDP_14b 0x05
+
+/* Receiver Capability */
+#define DP_DPCD_REV 0x000
+#define DP_DPCD_REV_10 0x10
+#define DP_DPCD_REV_11 0x11
+#define DP_DPCD_REV_12 0x12
+#define DP_DPCD_REV_13 0x13
+#define DP_DPCD_REV_14 0x14
+
+#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
+ DP_LANE_CHANNEL_EQ_DONE | \
+ DP_LANE_SYMBOL_LOCKED)
+
+#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
+#define DP_INTERLANE_ALIGN_DONE (1 << 0)
+#define DP_DOWNSTREAM_PORT_STATUS_CHANGED (1 << 6)
+#define DP_LINK_STATUS_UPDATED (1 << 7)
+
+#define DP_SINK_STATUS 0x205
+#define DP_RECEIVE_PORT_0_STATUS (1 << 0)
+#define DP_RECEIVE_PORT_1_STATUS (1 << 1)
+#define DP_STREAM_REGENERATION_STATUS (1 << 2)
+
+#define DP_AUX_MAX_PAYLOAD_BYTES 16
+
+#define MAX_LANECOUNT 4
+
+enum {
+ DP_LANECOUNT_1 = 0x1,
+ DP_LANECOUNT_2 = 0x2,
+ DP_LANECOUNT_4 = 0x4,
+};
+
+enum {
+ DP_VERSION_11 = 0x11,
+ DP_VERSION_12 = 0x12,
+ DP_VERSION_14 = 0x14,
+ DP_VERSION_12_14 = 0x16,
+ DP_VERSION_14_14 = 0x17,
+ DP_VERSION_MAX,
+};
+
+enum {
+ DPTX_SWING0 = 0x00,
+ DPTX_SWING1 = 0x01,
+ DPTX_SWING2 = 0x02,
+ DPTX_SWING3 = 0x03,
+};
+
+enum {
+ DPTX_PREEMPHASIS0 = 0x00,
+ DPTX_PREEMPHASIS1 = 0x01,
+ DPTX_PREEMPHASIS2 = 0x02,
+ DPTX_PREEMPHASIS3 = 0x03,
+};
+
+enum {
+ DPTX_PASS = 0,
+ DPTX_PLUG_OUT = 1,
+ DPTX_TIMEOUT = 2,
+ DPTX_AUTH_FAIL = 3,
+ DPTX_EDID_FAIL = 4,
+ DPTX_TRANING_FAIL = 5,
+ DPTX_TRANING_STATE_CHANGE = 6,
+};
+
+enum {
+ FEC_ERROR_COUNT_DISABLE = 0x0,
+ FEC_UNCORRECTED_BLOCK_ERROR_COUNT = 0x1,
+ FEC_CORRECTED_BLOCK_ERROR_COUNT = 0x2,
+ FEC_BIT_ERROR_COUNT = 0x3,
+ FEC_PARITY_BLOCK_ERROR_COUNT = 0x4,
+ FEC_PARITY_BIT_ERROR_COUNT = 0x5,
+};
+
+enum {
+ DPTX_NTSTATE_STARTUP = 0x0,
+ DPTX_NTSTATE_CHECKCAP = 0x1,
+ DPTX_NTSTATE_CHECKEDID = 0x2,
+ DPTX_NTSTATE_TRAINING_PRE = 0x3,
+ DPTX_NTSTATE_TRAINING = 0x4,
+ DPTX_NTSTATE_CHECKTIMING = 0x5,
+ DPTX_NTSTATE_NORMAL = 0x6,
+ DPTX_NTSTATE_POWERSAVE = 0x7,
+ DPTX_NTSTATE_DPIDLE = 0x8,
+ DPTX_NTSTATE_MAX,
+};
+
+enum {
+ DPTX_DISP_NONE = 0,
+ DPTX_DISP_RESUME = 1,
+ DPTX_DISP_SUSPEND = 2,
+};
+
+enum {
+ TRAIN_STEP_SUCCESS = 0,
+ TRAIN_STEP_FAIL_BREAK = 1,
+ TRAIN_STEP_FAIL_NOT_BREAK = 2,
+};
+
+#define DPTX_TRAIN_RETRY_LIMIT 0x8
+#define DPTX_TRAIN_MAX_ITERATION 0x5
+
+#define HPD_INT_EVNET BIT(3)
+#define HPD_CONNECT BIT(2)
+#define HPD_DISCONNECT BIT(1)
+#define HPD_INITIAL_STATE 0
+
+static bool dptx_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *data)
+{
+ u8 retry = 7;
+
+ do {
+ if (dptx_hal_auxwrite_bytes(mtk_dp, cmd,
+ dpcd_addr, length, data))
+ return true;
+
+ mdelay(1);
+ } while (--retry > 0);
+
+ printk(BIOS_ERR, "aux write fail: cmd = %d, addr = %#x, len = %ld\n",
+ cmd, dpcd_addr, length);
+
+ return false;
+}
+
+static bool dptx_auxwrite_dpcd(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *data)
+{
+ bool ret = true;
+ size_t offset = 0;
+ size_t len;
+
+ while (offset < length) {
+ len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES);
+ ret &= dptx_auxwrite_bytes(mtk_dp, cmd, dpcd_addr + offset,
+ len, data + offset);
+ offset += len;
+ }
+ return ret;
+}
+
+static bool dptx_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *data)
+{
+ u8 retry = 7;
+
+ do {
+ if (dptx_hal_auxread_bytes(mtk_dp, cmd,
+ dpcd_addr, length, data))
+ return true;
+
+ mdelay(1);
+ } while (--retry > 0);
+
+ printk(BIOS_ERR, "aux read fail: cmd = %d, addr = %#x, len = %ld\n",
+ cmd, dpcd_addr, length);
+
+ return false;
+}
+
+static bool dptx_auxread_dpcd(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *rxbuf)
+{
+ bool ret = true;
+ size_t offset = 0;
+ size_t len;
+
+ while (offset < length) {
+ len = MIN(length - offset, DP_AUX_MAX_PAYLOAD_BYTES);
+ ret &= dptx_auxread_bytes(mtk_dp, cmd, dpcd_addr + offset,
+ len, rxbuf + offset);
+ offset += len;
+ }
+ return ret;
+}
+
+static int dptx_get_edid(struct mtk_dp *mtk_dp, struct edid *out)
+{
+ int ret;
+ u8 edid[ONE_BLOCK_SIZE];
+ u8 tmp = 0;
+
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_I2C_WRITE, 0x50, 0x1, &tmp);
+
+ for (tmp = 0; tmp < ONE_BLOCK_SIZE / DP_AUX_MAX_PAYLOAD_BYTES; tmp++)
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_I2C_READ,
+ 0x50, DP_AUX_MAX_PAYLOAD_BYTES,
+ edid + tmp * 16);
+
+ ret = decode_edid(edid, ONE_BLOCK_SIZE, out);
+ if (ret != EDID_CONFORMANT) {
+ printk(BIOS_ERR, "failed to decode edid(%d).\n", ret);
+ return -1;
+ }
+
+ mtk_dp->edid = out;
+ return 0;
+}
+
+static u8 dptx_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
+{
+ return link_status[r - DP_LANE0_1_STATUS];
+}
+
+static u8 dptx_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane)
+{
+ int i = DP_LANE0_1_STATUS + (lane >> 1);
+ int s = (lane & 1) * 4;
+ u8 l = dptx_link_status(link_status, i);
+
+ return (l >> s) & 0xf;
+}
+
+static bool dptx_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane_count)
+{
+ int lane;
+ u8 lane_status;
+
+ for (lane = 0; lane < lane_count; lane++) {
+ lane_status = dptx_get_lane_status(link_status, lane);
+ if ((lane_status & DP_LANE_CR_DONE) == 0)
+ return false;
+ }
+ return true;
+}
+
+static void dptx_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u32 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ printk(BIOS_ERR, "aux interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
+ rd_interval = 1;
+ else
+ rd_interval *= 4;
+
+ mdelay(rd_interval);
+}
+
+static void dptx_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ u32 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+ DP_TRAINING_AUX_RD_MASK;
+
+ if (rd_interval > 4)
+ printk(BIOS_ERR, "aux interval %d, out of range (max 4)\n",
+ rd_interval);
+
+ if (rd_interval == 0)
+ rd_interval = 1;
+ else
+ rd_interval *= 4;
+
+ mdelay(rd_interval);
+}
+
+static bool dptx_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
+ int lane_count)
+{
+ u8 lane_align;
+ u8 lane_status;
+ int lane;
+
+ lane_align = dptx_link_status(link_status,
+ DP_LANE_ALIGN_STATUS_UPDATED);
+
+ if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
+ return false;
+
+ for (lane = 0; lane < lane_count; lane++) {
+ lane_status = dptx_get_lane_status(link_status, lane);
+ if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
+ return false;
+ }
+ return true;
+}
+
+static void dptx_videomute(struct mtk_dp *mtk_dp, bool enable)
+{
+ dptx_hal_videomute(mtk_dp, enable);
+}
+
+static void dptx_fec_ready(struct mtk_dp *mtk_dp, u8 err_cnt_sel)
+{
+ u8 i, data[3];
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ, 0x90, 0x1, data);
+ printk(BIOS_DEBUG, "FEC Capable[0], [0:3] should be 1: %#x\n",
+ data[0]);
+
+ /*
+ * FEC error count select 120[3:1]:
+ * 000b: FEC_ERROR_COUNT_DIS
+ * 001b: UNCORRECTED_BLOCK_ERROR_COUNT
+ * 010b: CORRECTED_BLOCK_ERROR_COUNT
+ * 011b: BIT_ERROR_COUNT
+ * 100b: PARITY_BLOCK_ERROR_COUNT
+ * 101b: PARITY_BIT_ERROR_COUNT
+ */
+ if (data[0] & BIT(0)) {
+ mtk_dp->has_fec = true;
+ data[0] = (err_cnt_sel << 1) | 0x1;
+
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ 0x120, 0x1, data);
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ 0x280, 0x3, data);
+
+ for (i = 0; i < 3; i++)
+ printk(BIOS_DEBUG, "FEC status & error Count: %#x\n",
+ data[i]);
+ }
+}
+
+static void dptx_init_variable(struct mtk_dp *mtk_dp)
+{
+ mtk_dp->regs = (void *)EDP_BASE;
+ mtk_dp->train_info.sys_max_linkrate = DP_LINKRATE_HBR3;
+ mtk_dp->train_info.linkrate = DP_LINKRATE_HBR2;
+ mtk_dp->train_info.linklane_count = DP_LANECOUNT_4;
+ mtk_dp->train_info.sink_extcap_en = false;
+ mtk_dp->train_info.sink_ssc_en = false;
+ mtk_dp->train_info.tps3 = true;
+ mtk_dp->train_info.tps4 = true;
+ mtk_dp->training_state = DPTX_NTSTATE_STARTUP;
+ mtk_dp->info.format = DP_COLOR_FORMAT_RGB_444;
+ mtk_dp->info.depth = DP_COLOR_DEPTH_8BIT;
+ mtk_dp->power_on = false;
+ mtk_dp->video_enable = false;
+ mtk_dp->dp_ready = false;
+ mtk_dp->has_dsc = false;
+ mtk_dp->has_fec = false;
+ mtk_dp->dsc_enable = false;
+}
+
+static inline bool dptx_check_res_sample_rate(const struct edid *edid)
+{
+ return edid->mode.va + edid->mode.vbl <= 525;
+}
+
+static void dptx_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 sram_read_start)
+{
+ u32 count = 0; /* count: sdp_down_cnt_init */
+ u8 offset;
+
+ if (mtk_dp->edid->mode.pixel_clock > 0)
+ count = (sram_read_start * 2700 * 8 *
+ mtk_dp->train_info.linkrate) /
+ (mtk_dp->edid->mode.pixel_clock * 4);
+
+ switch (mtk_dp->train_info.linklane_count) {
+ case DP_LANECOUNT_1:
+ count = (count > 0x1a) ? count : 0x1a;
+ break;
+ case DP_LANECOUNT_2:
+ /* Case for LowResolution and High Audio Sample Rate. */
+ offset = dptx_check_res_sample_rate(mtk_dp->edid) ?
+ 0x04 : 0x00;
+ count = (count > 0x10) ? count : 0x10 + offset;
+ break;
+ case DP_LANECOUNT_4:
+ default:
+ count = (count > 0x06) ? count : 0x06;
+ break;
+ }
+
+ printk(BIOS_DEBUG, "pixel rate(khz) = %d, sdp_dc_init = %#x\n",
+ mtk_dp->edid->mode.pixel_clock, count);
+
+ dptx_hal_setsdp_downcnt_init(mtk_dp, count);
+}
+
+static void dptx_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp)
+{
+ int pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000;
+ u8 offset;
+ u16 count = 0; /* count: sdp_down_cnt_init*/
+
+ switch (mtk_dp->train_info.linklane_count) {
+ case DP_LANECOUNT_1:
+ count = 0x20;
+ break;
+ case DP_LANECOUNT_2:
+ offset = dptx_check_res_sample_rate(mtk_dp->edid) ?
+ 0x14 : 0x00;
+ count = 0x0018 + offset;
+ break;
+ case DP_LANECOUNT_4:
+ default:
+ offset = dptx_check_res_sample_rate(mtk_dp->edid) ?
+ 0x08 : 0x00;
+ if (pixclk_mhz > mtk_dp->train_info.linkrate * 27) {
+ count = 0x8;
+ printk(BIOS_ERR, "ERROR: Pixclk > LinkRateChange\n");
+ } else {
+ count = 0x10 + offset;
+ }
+ break;
+ }
+
+ dptx_hal_setsdp_downcnt_init_inhblanking(mtk_dp, count);
+}
+
+static void dptx_set_tu(struct mtk_dp *mtk_dp)
+{
+ u8 bpp;
+ u16 sram_read_start = DPTX_TBC_BUF_READSTARTADRTHRD;
+ int tu_size, n_value, f_value, pixclk_mhz;
+
+ bpp = dptx_hal_get_colorbpp(mtk_dp);
+ pixclk_mhz = mtk_dp->edid->mode.pixel_clock / 1000;
+ tu_size = (640 * pixclk_mhz * bpp) /
+ (mtk_dp->train_info.linkrate * 27 *
+ mtk_dp->train_info.linklane_count * 8);
+
+ n_value = tu_size / 10;
+ f_value = tu_size % 10;
+ printk(BIOS_DEBUG, "TU_size %d, FValue %d\n", tu_size, f_value);
+
+ if (mtk_dp->train_info.linklane_count > 0) {
+ sram_read_start = mtk_dp->edid->mode.ha /
+ (mtk_dp->train_info.linklane_count *
+ 4 * 2 * 2);
+ sram_read_start = MIN(sram_read_start,
+ DPTX_TBC_BUF_READSTARTADRTHRD);
+ dptx_hal_settu_sramrd_start(mtk_dp, sram_read_start);
+ }
+
+ dptx_hal_settu_setencoder(mtk_dp);
+ dptx_setsdp_downcnt_init_inhblanking(mtk_dp);
+ dptx_setsdp_downcnt_init(mtk_dp, sram_read_start);
+}
+
+static void dptx_set_misc(struct mtk_dp *mtk_dp)
+{
+ u8 format, depth;
+ union misc_t dptx_misc;
+
+ format = mtk_dp->info.format;
+ depth = mtk_dp->info.depth;
+
+ /*
+ * MISC 0/1 reference to spec 1.4a p143 Table 2-96.
+ * MISC0[7:5] color depth.
+ */
+ dptx_misc.dp_misc.color_depth = depth;
+
+ /*
+ * MISC0[3]: 0->RGB, 1->YUV
+ * MISC0[2:1]: 01b->4:2:2, 10b->4:4:4
+ */
+ switch (format) {
+ case DP_COLOR_FORMAT_YUV_444:
+ dptx_misc.dp_misc.color_format = 0x1;
+ break;
+ case DP_COLOR_FORMAT_YUV_422:
+ dptx_misc.dp_misc.color_format = 0x2;
+ break;
+ case DP_COLOR_FORMAT_RAW:
+ dptx_misc.dp_misc.color_format = 0x1;
+ dptx_misc.dp_misc.spec_def2 = 0x1;
+ break;
+ case DP_COLOR_FORMAT_YONLY:
+ dptx_misc.dp_misc.color_format = 0x0;
+ dptx_misc.dp_misc.spec_def2 = 0x1;
+ break;
+ case DP_COLOR_FORMAT_YUV_420:
+ case DP_COLOR_FORMAT_RGB_444:
+ default:
+ break;
+ }
+
+ dptx_hal_setmisc(mtk_dp, dptx_misc.cmisc);
+}
+
+static void dptx_set_dptxout(struct mtk_dp *mtk_dp)
+{
+ dptx_hal_bypassmsa_en(mtk_dp, false);
+ dptx_set_tu(mtk_dp);
+}
+
+static bool dptx_training_checkswingpre(struct mtk_dp *mtk_dp,
+ u8 target_lane_count,
+ const u8 *dpcp202_x, u8 *dpcp_buf)
+{
+ bool ret = true;
+ u8 swing_value, preemphasis;
+
+ /* Lane 0 */
+ if (target_lane_count >= 0x1) {
+ swing_value = (dpcp202_x[4] & 0x3);
+ preemphasis = (dpcp202_x[4] & 0xc) >> 2;
+
+ /* Adjust the swing and pre-emphasis */
+ ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE0,
+ swing_value, preemphasis);
+
+ /*
+ * Adjust the swing and pre-emphasis done,
+ * and notify sink side.
+ */
+ dpcp_buf[0] = swing_value | (preemphasis << 3);
+
+ /* Max swing reached. */
+ if (swing_value == DPTX_SWING3)
+ dpcp_buf[0] |= BIT(2);
+
+ /* Max pre-emphasis reached. */
+ if (preemphasis == DPTX_PREEMPHASIS3)
+ dpcp_buf[0] |= BIT(5);
+ }
+
+ /* Lane 1 */
+ if (target_lane_count >= 0x2) {
+ swing_value = (dpcp202_x[4] & 0x30) >> 4;
+ preemphasis = (dpcp202_x[4] & 0xc0) >> 6;
+
+ /* Adjust the swing and pre-emphasis */
+ ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE1,
+ swing_value, preemphasis);
+
+ /*
+ * Adjust the swing and pre-emphasis done,
+ * and notify sink side.
+ */
+ dpcp_buf[1] = swing_value | (preemphasis << 3);
+
+ /* Max swing reached. */
+ if (swing_value == DPTX_SWING3)
+ dpcp_buf[1] |= BIT(2);
+
+ /* Max pre-emphasis reached. */
+ if (preemphasis == DPTX_PREEMPHASIS3)
+ dpcp_buf[1] |= BIT(5);
+ }
+
+ /* Lane 2 and Lane 3 */
+ if (target_lane_count == 0x4) {
+ /* Lane 2 */
+ swing_value = (dpcp202_x[5] & 0x3);
+ preemphasis = (dpcp202_x[5] & 0x0c) >> 2;
+
+ /* Adjust the swing and pre-emphasis */
+ ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE2,
+ swing_value, preemphasis);
+
+ /*
+ * Adjust the swing and pre-emphasis done,
+ * and notify sink side.
+ */
+ dpcp_buf[2] = swing_value | (preemphasis << 3);
+
+ /* Max swing reached. */
+ if (swing_value == DPTX_SWING3)
+ dpcp_buf[2] |= BIT(2);
+
+ /* Max pre-emphasis reached. */
+ if (preemphasis == DPTX_PREEMPHASIS3)
+ dpcp_buf[2] |= BIT(5);
+
+ /* Lane 3 */
+ swing_value = (dpcp202_x[5] & 0x30) >> 4;
+ preemphasis = (dpcp202_x[5] & 0xc0) >> 6;
+
+ /* Adjust the swing and pre-emphasis */
+ ret &= dptx_hal_setswing_preemphasis(mtk_dp, DPTX_LANE3,
+ swing_value, preemphasis);
+
+ /*
+ * Adjust the swing and pre-emphasis done,
+ * and notify sink side.
+ */
+ dpcp_buf[0x3] = swing_value | (preemphasis << 3);
+
+ /* Max swing reached. */
+ if (swing_value == DPTX_SWING3)
+ dpcp_buf[3] |= BIT(2);
+
+ /* Max pre-emphasis reached. */
+ if (preemphasis == DPTX_PREEMPHASIS3)
+ dpcp_buf[3] |= BIT(5);
+ }
+
+ /* Wait signal stable enough */
+ mdelay(2);
+
+ return ret;
+}
+
+static int dptx_train_tps1(struct mtk_dp *mtk_dp, u8 target_lanecount,
+ int *status_ctrl, int *iteration, u8 *dpcp_buffer,
+ u8 *dpcd206)
+{
+ u8 tmp_val[6];
+ u8 dpcd200c[3];
+
+ printk(BIOS_INFO, "CR Training START\n");
+ dptx_hal_setscramble(mtk_dp, false);
+
+ if (*status_ctrl == 0x0) {
+ dptx_hal_set_txtrainingpattern(mtk_dp, BIT(4));
+ *status_ctrl = 0x1;
+ tmp_val[0] = 0x21;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00102, 0x1, tmp_val);
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00206, 0x2, tmp_val + 4);
+ *iteration = *iteration + 1;
+
+ dptx_training_checkswingpre(mtk_dp, target_lanecount,
+ tmp_val, dpcp_buffer);
+ }
+
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00103, target_lanecount, dpcp_buffer);
+
+ dptx_link_train_clock_recovery_delay(mtk_dp->rx_cap);
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00202, 0x6, tmp_val);
+
+ if (mtk_dp->train_info.sink_extcap_en) {
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_0200C, 0x3, dpcd200c);
+ tmp_val[0] = dpcd200c[0];
+ tmp_val[1] = dpcd200c[1];
+ tmp_val[2] = dpcd200c[2];
+ }
+
+ if (dptx_clock_recovery_ok(tmp_val, target_lanecount)) {
+ printk(BIOS_INFO, "CR Training Success\n");
+
+ mtk_dp->train_info.cr_done = true;
+ *iteration = 0x1;
+
+ return TRAIN_STEP_SUCCESS;
+ }
+
+ printk(BIOS_INFO, "CR Training Fail\n");
+
+ /* Requested swing and emp is the same with last time. */
+ if (*dpcd206 == tmp_val[4]) {
+ *iteration = *iteration + 1;
+ if (*dpcd206 & 0x3)
+ return TRAIN_STEP_FAIL_BREAK;
+ } else {
+ *dpcd206 = tmp_val[4];
+ }
+
+ return TRAIN_STEP_FAIL_NOT_BREAK;
+}
+
+static int dptx_train_tps2_3(struct mtk_dp *mtk_dp, u8 target_lanecount,
+ int *status_ctrl, int *iteration, u8 *dpcp_buffer,
+ u8 *dpcd206)
+{
+ u8 tmp_val[6];
+ u8 dpcd200c[3];
+
+ printk(BIOS_INFO, "EQ Training START\n");
+
+ if (*status_ctrl == 0x1) {
+ if (mtk_dp->train_info.tps4)
+ dptx_hal_set_txtrainingpattern(mtk_dp, BIT(7));
+ else if (mtk_dp->train_info.tps3)
+ dptx_hal_set_txtrainingpattern(mtk_dp, BIT(6));
+ else
+ dptx_hal_set_txtrainingpattern(mtk_dp, BIT(5));
+
+ if (mtk_dp->train_info.tps4) {
+ tmp_val[0] = 0x07;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00102, 0x1, tmp_val);
+ } else if (mtk_dp->train_info.tps3) {
+ tmp_val[0] = 0x23;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00102, 0x1, tmp_val);
+ } else {
+ tmp_val[0] = 0x22;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00102, 0x1, tmp_val);
+ }
+
+ *status_ctrl = 0x2;
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00206, 0x2, tmp_val + 4);
+
+ *iteration = *iteration + 1;
+ dptx_training_checkswingpre(mtk_dp, target_lanecount,
+ tmp_val, dpcp_buffer);
+ }
+
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE, DPCD_00103,
+ target_lanecount, dpcp_buffer);
+ dptx_link_train_channel_eq_delay(mtk_dp->rx_cap);
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00202, 0x6, tmp_val);
+
+ if (mtk_dp->train_info.sink_extcap_en) {
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_0200C, 0x3, dpcd200c);
+ tmp_val[0] |= dpcd200c[0];
+ tmp_val[1] |= dpcd200c[1];
+ tmp_val[2] |= dpcd200c[2];
+ }
+
+ if (!dptx_clock_recovery_ok(tmp_val, target_lanecount)) {
+ printk(BIOS_INFO, "EQ Training Fail\n");
+ mtk_dp->train_info.cr_done = false;
+ mtk_dp->train_info.eq_done = false;
+ return TRAIN_STEP_FAIL_BREAK;
+ }
+
+ if (dptx_channel_eq_ok(tmp_val, target_lanecount)) {
+ printk(BIOS_INFO, "EQ Training Success\n");
+ mtk_dp->train_info.eq_done = true;
+ return TRAIN_STEP_SUCCESS;
+ }
+ printk(BIOS_INFO, "EQ Training Fail\n");
+
+ if (*dpcd206 == tmp_val[4])
+ *iteration = *iteration + 1;
+ else
+ *dpcd206 = tmp_val[4];
+
+ return TRAIN_STEP_FAIL_NOT_BREAK;
+}
+
+static int dptx_trainingflow(struct mtk_dp *mtk_dp,
+ u8 lanerate, u8 lanecount)
+{
+ u8 tmp_val[6];
+ u8 target_linkrate = lanerate;
+ u8 target_lanecount = lanecount;
+ u8 dpcp_buffer[4];
+ u8 dpcd206;
+ bool pass_tps1 = false;
+ bool pass_tps2_3 = false;
+ int train_retry, status_ctrl, iteration;
+
+ memset(tmp_val, 0, sizeof(tmp_val));
+ memset(dpcp_buffer, 0, sizeof(dpcp_buffer));
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00600, 0x1, tmp_val);
+ if (tmp_val[0] != 0x1) {
+ tmp_val[0] = 0x1;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00600, 0x1, tmp_val);
+ mdelay(1);
+ }
+
+ tmp_val[0] = target_linkrate;
+ tmp_val[1] = target_lanecount | DPTX_AUX_SET_ENAHNCED_FRAME;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00100, 0x2, tmp_val);
+
+ if (mtk_dp->train_info.sink_ssc_en) {
+ tmp_val[0x0] = 0x10;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00107, 0x1, tmp_val);
+ }
+
+ train_retry = 0x0;
+ status_ctrl = 0x0;
+ iteration = 0x1;
+ dpcd206 = 0xff;
+
+ dptx_hal_set_txlane(mtk_dp, target_lanecount / 2);
+ dptx_hal_set_txrate(mtk_dp, target_linkrate);
+
+ do {
+ train_retry++;
+ if (!pass_tps1) {
+ int ret = dptx_train_tps1(mtk_dp, target_lanecount,
+ &status_ctrl, &iteration,
+ dpcp_buffer, &dpcd206);
+ if (ret == TRAIN_STEP_FAIL_BREAK)
+ break;
+ if (ret == TRAIN_STEP_SUCCESS) {
+ pass_tps1 = true;
+ train_retry = 0;
+ }
+ } else {
+ int ret = dptx_train_tps2_3(mtk_dp, target_lanecount,
+ &status_ctrl, &iteration,
+ dpcp_buffer, &dpcd206);
+ if (ret == TRAIN_STEP_FAIL_BREAK)
+ break;
+ if (ret == TRAIN_STEP_SUCCESS) {
+ pass_tps2_3 = true;
+ break;
+ }
+ }
+
+ dptx_training_checkswingpre(mtk_dp, target_lanecount,
+ tmp_val, dpcp_buffer);
+
+ } while (train_retry < DPTX_TRAIN_RETRY_LIMIT &&
+ iteration < DPTX_TRAIN_MAX_ITERATION);
+
+ tmp_val[0] = 0x0;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00102, 0x1, tmp_val);
+ dptx_hal_set_txtrainingpattern(mtk_dp, 0);
+
+ if (!pass_tps2_3) {
+ printk(BIOS_ERR, "Link Training Fail\n");
+ return DPTX_TRANING_FAIL;
+ }
+
+ mtk_dp->train_info.linkrate = target_linkrate;
+ mtk_dp->train_info.linklane_count = target_lanecount;
+
+ dptx_hal_setscramble(mtk_dp, true);
+
+ tmp_val[0] = target_lanecount | DPTX_AUX_SET_ENAHNCED_FRAME;
+
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00101, 0x1, tmp_val);
+ dptx_hal_set_ef_mode(mtk_dp, ENABLE_DPTX_EF_MODE);
+
+ printk(BIOS_INFO, "Link Training Success\n");
+ return DPTX_PASS;
+}
+
+static void dptx_check_sinkcap(struct mtk_dp *mtk_dp)
+{
+ u8 buffer[16];
+
+ memset(buffer, 0x0, sizeof(buffer));
+
+ buffer[0] = 0x1;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00600, 0x1, buffer);
+
+ mdelay(2);
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00000, 0x10, buffer);
+
+ mtk_dp->train_info.sink_extcap_en = false;
+ mtk_dp->train_info.dpcd_rev = buffer[0];
+
+ printk(BIOS_INFO, "SINK DPCD version: %#x\n",
+ mtk_dp->train_info.dpcd_rev);
+
+ memcpy(mtk_dp->rx_cap, buffer, sizeof(mtk_dp->rx_cap));
+
+ mtk_dp->rx_cap[14] &= 0x7f;
+
+ if (mtk_dp->train_info.dpcd_rev >= 0x14)
+ dptx_fec_ready(mtk_dp, FEC_BIT_ERROR_COUNT);
+
+ mtk_dp->train_info.linkrate = MIN(buffer[0x1],
+ mtk_dp->train_info.sys_max_linkrate);
+ mtk_dp->train_info.linklane_count = MIN(buffer[2] & 0x1F,
+ MAX_LANECOUNT);
+
+ mtk_dp->train_info.tps3 = (buffer[2] & BIT(6)) >> 0x6;
+ mtk_dp->train_info.tps4 = (buffer[3] & BIT(7)) >> 0x7;
+
+ mtk_dp->train_info.down_stream_port_present = (buffer[5] & BIT(0));
+
+ if ((buffer[3] & BIT(0)) == 0x1) {
+ printk(BIOS_INFO, "SINK SUPPORT SSC!\n");
+ mtk_dp->train_info.sink_ssc_en = true;
+ } else {
+ printk(BIOS_INFO, "SINK NOT SUPPORT SSC!\n");
+ mtk_dp->train_info.sink_ssc_en = false;
+ }
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00021, 0x1, buffer);
+ mtk_dp->train_info.dp_mstcap = (buffer[0] & BIT(0));
+ mtk_dp->train_info.dp_mstbranch = false;
+
+ if (mtk_dp->train_info.dp_mstcap == BIT(0)) {
+ if (mtk_dp->train_info.down_stream_port_present == 0x1)
+ mtk_dp->train_info.dp_mstbranch = true;
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_02003, 0x1, buffer);
+ if (buffer[0] != 0x0)
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_02003, 0x1, buffer);
+ }
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00600, 0x1, buffer);
+ if (buffer[0] != 0x1) {
+ buffer[0] = 0x1;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00600, 0x1, buffer);
+ }
+
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00200, 0x2, buffer);
+}
+
+static void dptx_training_changemode(struct mtk_dp *mtk_dp)
+{
+ dptx_hal_phyd_reset(mtk_dp);
+ dptx_hal_reset_swing_preemphasis(mtk_dp);
+ dptx_hal_ssc_en(mtk_dp, mtk_dp->train_info.sink_ssc_en);
+
+ mdelay(2);
+}
+
+static int dptx_set_trainingstart(struct mtk_dp *mtk_dp)
+{
+ int ret = DPTX_PASS;
+ u8 lanecount;
+ u8 linkrate;
+ u8 buffer;
+ u8 limit;
+ u8 max_linkrate;
+
+ buffer = 0x1;
+ dptx_auxwrite_dpcd(mtk_dp, DP_AUX_NATIVE_WRITE,
+ DPCD_00600, 0x1, &buffer);
+
+ linkrate = mtk_dp->rx_cap[1];
+ lanecount = mtk_dp->rx_cap[2] & 0x1f;
+
+ printk(BIOS_INFO, "RX support linkrate = %#x, lanecount = %#x\n",
+ linkrate, lanecount);
+
+ mtk_dp->train_info.linkrate =
+ (linkrate >= mtk_dp->train_info.sys_max_linkrate) ?
+ mtk_dp->train_info.sys_max_linkrate : linkrate;
+ mtk_dp->train_info.linklane_count = (lanecount >= MAX_LANECOUNT) ?
+ MAX_LANECOUNT : lanecount;
+
+ if (mtk_dp->train_info.sink_extcap_en)
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_02002, 0x1, &buffer);
+ else
+ dptx_auxread_dpcd(mtk_dp, DP_AUX_NATIVE_READ,
+ DPCD_00200, 0x1, &buffer);
+
+ if ((buffer & 0xbf) != 0)
+ mtk_dp->train_info.sink_count_num = buffer & 0xbf;
+
+ linkrate = mtk_dp->train_info.linkrate;
+ lanecount = mtk_dp->train_info.linklane_count;
+
+ switch (linkrate) {
+ case DP_LINKRATE_RBR:
+ case DP_LINKRATE_HBR:
+ case DP_LINKRATE_HBR2:
+ case DP_LINKRATE_HBR25:
+ case DP_LINKRATE_HBR3:
+ break;
+ default:
+ mtk_dp->train_info.linkrate = DP_LINKRATE_HBR3;
+ break;
+ };
+
+ max_linkrate = linkrate;
+ limit = 0x6;
+
+ do {
+ mtk_dp->train_info.cr_done = false;
+ mtk_dp->train_info.eq_done = false;
+
+ dptx_training_changemode(mtk_dp);
+ ret = dptx_trainingflow(mtk_dp, linkrate, lanecount);
+
+ if (!mtk_dp->train_info.cr_done) {
+ /* CR fail and reduce link capability. */
+ switch (linkrate) {
+ case DP_LINKRATE_RBR:
+ lanecount = lanecount / 2;
+ linkrate = max_linkrate;
+
+ if (lanecount == 0x0)
+ return DPTX_TRANING_FAIL;
+ break;
+ case DP_LINKRATE_HBR:
+ linkrate = DP_LINKRATE_RBR;
+ break;
+ case DP_LINKRATE_HBR2:
+ linkrate = DP_LINKRATE_HBR;
+ break;
+ case DP_LINKRATE_HBR3:
+ linkrate = DP_LINKRATE_HBR2;
+ break;
+ default:
+ return DPTX_TRANING_FAIL;
+ };
+ } else if (!mtk_dp->train_info.eq_done) {
+ /* EQ fail and reduce lane counts. */
+ if (lanecount == DP_LANECOUNT_4)
+ lanecount = DP_LANECOUNT_2;
+ else if (lanecount == DP_LANECOUNT_2)
+ lanecount = DP_LANECOUNT_1;
+ else
+ return DPTX_TRANING_FAIL;
+ } else {
+ return DPTX_PASS;
+ }
+ } while (--limit > 0);
+
+ return DPTX_TRANING_FAIL;
+}
+
+static void dptx_init_port(struct mtk_dp *mtk_dp)
+{
+ dptx_hal_phy_setidlepattern(mtk_dp, true);
+ dptx_hal_init_setting(mtk_dp);
+ dptx_hal_aux_setting(mtk_dp);
+ dptx_hal_digital_setting(mtk_dp);
+ dptx_hal_phy_setting(mtk_dp);
+ dptx_hal_hpd_detect_setting(mtk_dp);
+
+ dptx_hal_digital_swreset(mtk_dp);
+ dptx_hal_analog_power_en(mtk_dp, true);
+ dptx_hal_hpd_int_en(mtk_dp, true);
+}
+
+static void dptx_video_enable(struct mtk_dp *mtk_dp, bool enable)
+{
+ printk(BIOS_INFO, "Output Video %s!\n", enable ?
+ "enable" : "disable");
+
+ if (enable) {
+ dptx_set_dptxout(mtk_dp);
+ dptx_videomute(mtk_dp, false);
+ dptx_hal_verify_clock(mtk_dp);
+ } else
+ dptx_videomute(mtk_dp, true);
+}
+
+static void dptx_set_color_format(struct mtk_dp *mtk_dp, u8 color_format)
+{
+ dptx_hal_set_color_format(mtk_dp, color_format);
+}
+
+static void dptx_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth)
+{
+ dptx_hal_set_color_depth(mtk_dp, color_depth);
+}
+
+static void dptx_video_config(struct mtk_dp *mtk_dp)
+{
+ u32 mvid = 0;
+ bool overwrite = false;
+
+ dptx_hal_overwrite_mn(mtk_dp, overwrite, mvid, 0x8000);
+
+ /* Interlace does not support. */
+ dptx_hal_set_msa(mtk_dp);
+ dptx_set_misc(mtk_dp);
+ dptx_set_color_depth(mtk_dp, mtk_dp->info.depth);
+ dptx_set_color_format(mtk_dp, mtk_dp->info.format);
+}
+
+int mtk_edp_init(struct edid *edid)
+{
+ struct mtk_dp mtk_edp;
+
+ dptx_init_variable(&mtk_edp);
+ dptx_init_port(&mtk_edp);
+
+ if (!dptx_hal_hpd_high(&mtk_edp)) {
+ printk(BIOS_ERR, "HPD is low\n");
+ return -1;
+ }
+
+ dptx_check_sinkcap(&mtk_edp);
+
+ dptx_get_edid(&mtk_edp, edid);
+
+ dptx_set_trainingstart(&mtk_edp);
+ dp_intf_config(edid);
+ dptx_video_config(&mtk_edp);
+ dptx_video_enable(&mtk_edp, true);
+
+ return 0;
+}
diff --git a/src/soc/mediatek/mt8195/dptx_hal.c b/src/soc/mediatek/mt8195/dptx_hal.c
new file mode 100644
index 0000000..6c6143a
--- /dev/null
+++ b/src/soc/mediatek/mt8195/dptx_hal.c
@@ -0,0 +1,826 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <delay.h>
+#include <edid.h>
+#include <soc/dptx.h>
+#include <soc/dptx_hal.h>
+#include <soc/dptx_reg.h>
+#include <string.h>
+#include <timer.h>
+
+#define REG_OFFSET_LIMIT 0x8000
+
+struct shift_mask {
+ u32 shift;
+ u32 mask;
+};
+static const struct shift_mask volt_swing[DPTX_LANE_MAX] = {
+ [DPTX_LANE0] = { DP_TX0_VOLT_SWING_FLDMASK_POS, DP_TX0_VOLT_SWING_FLDMASK },
+ [DPTX_LANE1] = { DP_TX1_VOLT_SWING_FLDMASK_POS, DP_TX1_VOLT_SWING_FLDMASK },
+ [DPTX_LANE2] = { DP_TX2_VOLT_SWING_FLDMASK_POS, DP_TX2_VOLT_SWING_FLDMASK },
+ [DPTX_LANE3] = { DP_TX3_VOLT_SWING_FLDMASK_POS, DP_TX3_VOLT_SWING_FLDMASK },
+};
+static const struct shift_mask volt_preemphasis[DPTX_LANE_MAX] = {
+ [DPTX_LANE0] = { DP_TX0_PRE_EMPH_FLDMASK_POS, DP_TX0_PRE_EMPH_FLDMASK },
+ [DPTX_LANE1] = { DP_TX1_PRE_EMPH_FLDMASK_POS, DP_TX1_PRE_EMPH_FLDMASK },
+ [DPTX_LANE2] = { DP_TX2_PRE_EMPH_FLDMASK_POS, DP_TX2_PRE_EMPH_FLDMASK },
+ [DPTX_LANE3] = { DP_TX3_PRE_EMPH_FLDMASK_POS, DP_TX3_PRE_EMPH_FLDMASK },
+};
+
+u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)
+{
+ void *addr = mtk_dp->regs + offset;
+
+ if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) {
+ printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n",
+ __func__, offset, mtk_dp->regs);
+ return 0;
+ }
+
+ return read32(addr);
+}
+
+void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
+{
+ void *addr = mtk_dp->regs + offset;
+
+ if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) {
+ printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n",
+ __func__, offset, mtk_dp->regs);
+ return;
+ }
+
+ write32(addr, val);
+}
+
+void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask)
+{
+ void *addr = mtk_dp->regs + offset;
+
+ if (offset % 4 != 0 || offset > REG_OFFSET_LIMIT) {
+ printk(BIOS_ERR, "[%s] invalid offset %#x for reg %p\n",
+ __func__, offset, mtk_dp->regs);
+ return;
+ }
+
+ /*
+ * TODO: modify to clrsetbits32(addr, mask, val);
+ * There is asserion error when testing assert((val & mask) == val).
+ */
+ clrsetbits32(addr, mask, val & mask);
+}
+
+void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask)
+{
+ if (addr % 2) {
+ mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x12);
+ mtk_dp_mask(mtk_dp, addr - 1, val << 8, mask << 8);
+ } else {
+ mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x11);
+ mtk_dp_mask(mtk_dp, addr, val, mask);
+ }
+
+ mtk_dp_write(mtk_dp, DP_TX_TOP_APB_WSTRB, 0x0);
+}
+
+void dptx_hal_verify_clock(struct mtk_dp *mtk_dp)
+{
+ u32 m, n, ls_clk, pix_clk;
+
+ m = mtk_dp_read(mtk_dp, REG_33C8_DP_ENCODER1_P0);
+ n = 0x8000;
+ ls_clk = mtk_dp->train_info.linkrate;
+ ls_clk *= 27;
+
+ pix_clk = m * ls_clk / n;
+ printk(BIOS_DEBUG, "DPTX calc pixel clock = %d MHz, dp_intf clock = %dMHz\n",
+ pix_clk, pix_clk / 4);
+}
+
+void dptx_hal_init_setting(struct mtk_dp *mtk_dp)
+{
+ DP_WRITE1BYTE(mtk_dp, REG_342C_DP_TRANS_P0, 0x69);
+ mtk_dp_mask(mtk_dp, REG_3540_DP_TRANS_P0, BIT(3), BIT(3));
+ mtk_dp_mask(mtk_dp, REG_31EC_DP_ENCODER0_P0, BIT(4), BIT(4));
+ mtk_dp_mask(mtk_dp, REG_304C_DP_ENCODER0_P0, 0, BIT(8));
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_IRQ_MASK, BIT(2), BIT(2));
+}
+
+void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_mask(mtk_dp, REG_3030_DP_ENCODER0_P0,
+ enable ? 0 : 0x3ff, 0x3ff);
+}
+
+void dptx_hal_set_msa(struct mtk_dp *mtk_dp)
+{
+ u32 va, vsync, vbp, vfp, vtotal, ha, hsync, hbp, hfp, htotal;
+ struct edid *edid = mtk_dp->edid;
+
+ va = edid->mode.va;
+ vsync = edid->mode.vspw;
+ vbp = edid->mode.vbl - edid->mode.vso -
+ edid->mode.vspw - edid->mode.vborder;
+ vfp = edid->mode.vso - edid->mode.vborder;
+
+ ha = edid->mode.ha;
+ hsync = edid->mode.hspw;
+ hbp = edid->mode.hbl - edid->mode.hso -
+ edid->mode.hspw - edid->mode.hborder;
+ hfp = edid->mode.hso - edid->mode.hborder;
+
+ htotal = ha + hsync + hbp + hfp;
+ vtotal = va + vsync + vbp + vfp;
+
+ DP_WRITE2BYTE(mtk_dp, REG_3010_DP_ENCODER0_P0, htotal);
+ DP_WRITE2BYTE(mtk_dp, REG_3018_DP_ENCODER0_P0, hsync + hbp);
+ mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0,
+ hsync << HSW_SW_DP_ENCODER0_P0_FLDMASK_POS,
+ HSW_SW_DP_ENCODER0_P0_FLDMASK);
+ mtk_dp_mask(mtk_dp, REG_3028_DP_ENCODER0_P0,
+ 0 << HSP_SW_DP_ENCODER0_P0_FLDMASK_POS,
+ HSP_SW_DP_ENCODER0_P0_FLDMASK);
+ DP_WRITE2BYTE(mtk_dp, REG_3020_DP_ENCODER0_P0, ha);
+ DP_WRITE2BYTE(mtk_dp, REG_3014_DP_ENCODER0_P0, va);
+ DP_WRITE2BYTE(mtk_dp, REG_301C_DP_ENCODER0_P0, vsync + vbp);
+ mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0,
+ vsync << VSW_SW_DP_ENCODER0_P0_FLDMASK_POS,
+ VSW_SW_DP_ENCODER0_P0_FLDMASK);
+ mtk_dp_mask(mtk_dp, REG_302C_DP_ENCODER0_P0,
+ 0 << VSP_SW_DP_ENCODER0_P0_FLDMASK_POS,
+ VSP_SW_DP_ENCODER0_P0_FLDMASK);
+ DP_WRITE2BYTE(mtk_dp, REG_3024_DP_ENCODER0_P0, va);
+ DP_WRITE2BYTE(mtk_dp, REG_3064_DP_ENCODER0_P0, ha);
+ DP_WRITE2BYTE(mtk_dp, REG_3154_DP_ENCODER0_P0, htotal);
+ DP_WRITE2BYTE(mtk_dp, REG_3158_DP_ENCODER0_P0, hfp);
+ DP_WRITE2BYTE(mtk_dp, REG_315C_DP_ENCODER0_P0, vsync);
+ DP_WRITE2BYTE(mtk_dp, REG_3160_DP_ENCODER0_P0, hsync + hbp);
+ DP_WRITE2BYTE(mtk_dp, REG_3164_DP_ENCODER0_P0, ha);
+ DP_WRITE2BYTE(mtk_dp, REG_3168_DP_ENCODER0_P0, vtotal);
+ DP_WRITE2BYTE(mtk_dp, REG_316C_DP_ENCODER0_P0, hfp);
+ DP_WRITE2BYTE(mtk_dp, REG_3170_DP_ENCODER0_P0, vsync);
+ DP_WRITE2BYTE(mtk_dp, REG_3174_DP_ENCODER0_P0, vsync + vbp);
+ DP_WRITE2BYTE(mtk_dp, REG_3178_DP_ENCODER0_P0, va);
+
+ printk(BIOS_INFO, "MSA:Htt(%d), Vtt(%d), Hact(%d), Vact(%d), FPS(%d)\n",
+ htotal, vtotal, ha, va,
+ edid->mode.pixel_clock * 1000 / htotal / vtotal);
+}
+
+void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 out_format)
+{
+ /* MISC0 */
+ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0,
+ out_format << 0x1, MASKBIT(2, 1));
+
+ switch (out_format) {
+ case DP_COLOR_FORMAT_RGB_444:
+ case DP_COLOR_FORMAT_YUV_444:
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1,
+ 0, MASKBIT(6, 4));
+ break;
+ case DP_COLOR_FORMAT_YUV_422:
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1,
+ BIT(4), MASKBIT(6, 4));
+ break;
+ case DP_COLOR_FORMAT_YUV_420:
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, BIT(5),
+ MASKBIT(6, 4));
+ break;
+ default:
+ break;
+ }
+}
+
+void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth)
+{
+ u8 val;
+
+ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0,
+ color_depth << 0x5, 0xe0);
+
+ switch (color_depth) {
+ case DP_COLOR_DEPTH_6BIT:
+ val = 4;
+ break;
+ case DP_COLOR_DEPTH_8BIT:
+ val = 3;
+ break;
+ case DP_COLOR_DEPTH_10BIT:
+ val = 2;
+ break;
+ case DP_COLOR_DEPTH_12BIT:
+ val = 1;
+ break;
+ case DP_COLOR_DEPTH_16BIT:
+ val = 0;
+ break;
+ default:
+ return;
+ }
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1, val, 0x7);
+}
+
+void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2])
+{
+ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0, cmisc[0], 0xfe);
+ mtk_dp_write_byte(mtk_dp, REG_3034_DP_ENCODER0_P0 + 1, cmisc[1], 0xff);
+}
+
+void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp,
+ bool enable, u32 video_m, u32 video_n)
+{
+ if (enable) {
+ /* Turn on overwrite MN */
+ DP_WRITE2BYTE(mtk_dp, REG_3008_DP_ENCODER0_P0,
+ video_m & 0xffff);
+ DP_WRITE1BYTE(mtk_dp, REG_300C_DP_ENCODER0_P0,
+ (video_m >> 16) & 0xff);
+ DP_WRITE2BYTE(mtk_dp, REG_3044_DP_ENCODER0_P0,
+ video_n & 0xffff);
+ DP_WRITE1BYTE(mtk_dp, REG_3048_DP_ENCODER0_P0,
+ (video_n >> 16) & 0xff);
+ DP_WRITE2BYTE(mtk_dp, REG_3050_DP_ENCODER0_P0,
+ video_n & 0xffff);
+
+ /* Add legerII. */
+ DP_WRITE1BYTE(mtk_dp, REG_3054_DP_ENCODER0_P0,
+ (video_n >> 16) & 0xff);
+ mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1,
+ BIT(0), BIT(0));
+ } else {
+ /* Turn off overwrite MN */
+ mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1,
+ 0, BIT(0));
+ }
+}
+
+u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp)
+{
+ u8 color_bpp;
+ u8 color_depth = mtk_dp->info.depth;
+ u8 color_format = mtk_dp->info.format;
+
+ switch (color_depth) {
+ case DP_COLOR_DEPTH_6BIT:
+ if (color_format == DP_COLOR_FORMAT_YUV_422)
+ color_bpp = 16;
+ else if (color_format == DP_COLOR_FORMAT_YUV_420)
+ color_bpp = 12;
+ else
+ color_bpp = 18;
+ break;
+ case DP_COLOR_DEPTH_8BIT:
+ if (color_format == DP_COLOR_FORMAT_YUV_422)
+ color_bpp = 16;
+ else if (color_format == DP_COLOR_FORMAT_YUV_420)
+ color_bpp = 12;
+ else
+ color_bpp = 24;
+ break;
+ case DP_COLOR_DEPTH_10BIT:
+ if (color_format == DP_COLOR_FORMAT_YUV_422)
+ color_bpp = 20;
+ else if (color_format == DP_COLOR_FORMAT_YUV_420)
+ color_bpp = 15;
+ else
+ color_bpp = 30;
+ break;
+ case DP_COLOR_DEPTH_12BIT:
+ if (color_format == DP_COLOR_FORMAT_YUV_422)
+ color_bpp = 24;
+ else if (color_format == DP_COLOR_FORMAT_YUV_420)
+ color_bpp = 18;
+ else
+ color_bpp = 36;
+ break;
+ case DP_COLOR_DEPTH_16BIT:
+ if (color_format == DP_COLOR_FORMAT_YUV_422)
+ color_bpp = 32;
+ else if (color_format == DP_COLOR_FORMAT_YUV_420)
+ color_bpp = 24;
+ else
+ color_bpp = 48;
+ break;
+ default:
+ color_bpp = 24;
+ printk(BIOS_ERR, "Set wrong bpp = %d\n", color_bpp);
+ break;
+ }
+
+ return color_bpp;
+}
+
+void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value)
+{
+ /*
+ * [5:0] video sram start address
+ * modify in 480P case only, default=0x1f
+ */
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0, (u8)value, 0x3f);
+}
+
+void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value)
+{
+ mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, value, 0xfff);
+
+}
+
+void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value)
+{
+ mtk_dp_mask(mtk_dp, REG_3040_DP_ENCODER0_P0, value, 0xfff);
+}
+
+void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write_byte(mtk_dp, REG_303C_DP_ENCODER0_P0 + 1,
+ BIT(7), BIT(7));
+ DP_WRITE2BYTE(mtk_dp, REG_3040_DP_ENCODER0_P0, 0x2020);
+ mtk_dp_mask(mtk_dp, REG_3364_DP_ENCODER1_P0, 0x2020, 0xfff);
+ mtk_dp_write_byte(mtk_dp, REG_3300_DP_ENCODER1_P0 + 1,
+ 0x2, BIT(1) | BIT(0));
+ mtk_dp_write_byte(mtk_dp, REG_3364_DP_ENCODER1_P0 + 1,
+ 0x40, 0x70);
+ DP_WRITE2BYTE(mtk_dp, REG_3368_DP_ENCODER1_P0, 0x1111);
+}
+
+bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp)
+{
+ return mtk_dp_read(mtk_dp, REG_3414_DP_TRANS_P0) & BIT(2);
+}
+
+bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *rx_buf)
+{
+ bool valid_cmd = false;
+ u8 reply_cmd, aux_irq_status;
+ int rd_count;
+ u32 wait_reply_count = AUX_WAITREPLY_LPNUM;
+
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+ mdelay(1);
+
+ if (length > 16 || (cmd == AUX_CMD_NATIVE_R && length == 0x0))
+ return false;
+
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1);
+ DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd);
+ DP_WRITE2BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xffff);
+ DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0, (dpcd_addr >> 16) & 0xf);
+
+ if (length > 0) {
+ mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0,
+ (length - 1) << MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS,
+ MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK);
+ DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0);
+ }
+
+ if (cmd == AUX_CMD_I2C_R || cmd == AUX_CMD_I2C_R_MOT0)
+ if (length == 0x0)
+ mtk_dp_mask(mtk_dp, REG_362C_AUX_TX_P0,
+ 0x1 << AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS,
+ AUX_NO_LENGTH_AUX_TX_P0_FLDMASK);
+
+ mtk_dp_mask(mtk_dp, REG_3630_AUX_TX_P0,
+ 0x1 << AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS,
+ AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK);
+
+ while (--wait_reply_count) {
+ if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) &
+ AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK) {
+ valid_cmd = true;
+ break;
+ }
+
+ if (mtk_dp_read(mtk_dp, REG_3618_AUX_TX_P0) &
+ AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK) {
+ valid_cmd = true;
+ break;
+ }
+
+ aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff;
+
+ if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) {
+ valid_cmd = true;
+ break;
+ }
+
+ if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK) {
+ printk(BIOS_ERR, "(AUX Read)HW Timeout 400us irq\n");
+ break;
+ }
+ }
+
+ reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf;
+ if (reply_cmd)
+ printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd);
+
+ if (wait_reply_count == 0x0 || reply_cmd) {
+ u8 phy_status = 0x0;
+
+ phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0);
+ if (phy_status != 0x1)
+ printk(BIOS_ERR, "Aux read: aux hang, need sw reset\n");
+
+ mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0,
+ 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS,
+ MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK);
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+
+ mdelay(1);
+ printk(BIOS_ERR, "wait_reply_count(%#x), TimeOut\n",
+ wait_reply_count);
+ return false;
+ }
+
+ if (length == 0) {
+ DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0);
+ } else {
+ if (valid_cmd) {
+ mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0,
+ 0x0 << AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS,
+ AUX_RD_MODE_AUX_TX_P0_FLDMASK);
+
+ for (rd_count = 0; rd_count < length; rd_count++) {
+ mtk_dp_mask(mtk_dp, REG_3620_AUX_TX_P0,
+ 0x1 << AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS,
+ AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK);
+ mdelay(1);
+ *(rx_buf + rd_count) = mtk_dp_read(mtk_dp,
+ REG_3620_AUX_TX_P0);
+ }
+ } else {
+ printk(BIOS_INFO, "Read TimeOut %#x\n", dpcd_addr);
+ }
+ }
+
+ mtk_dp_mask(mtk_dp, REG_3650_AUX_TX_P0,
+ 0x1 << MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS,
+ MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK);
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+
+ mdelay(1);
+ return valid_cmd;
+}
+
+bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *data)
+{
+ bool valid_cmd = false;
+ u8 reply_cmd;
+ int i;
+ u16 wait_reply_count = AUX_WAITREPLY_LPNUM;
+ int reg_idx;
+
+ mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0,
+ 1 << AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS,
+ AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK);
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1);
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+ mdelay(1);
+
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1);
+ DP_WRITE1BYTE(mtk_dp, REG_3644_AUX_TX_P0, cmd);
+ DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0, dpcd_addr & 0xff);
+ DP_WRITE1BYTE(mtk_dp, REG_3648_AUX_TX_P0 + 1,
+ (dpcd_addr >> 8) & 0xff);
+ DP_WRITE1BYTE(mtk_dp, REG_364C_AUX_TX_P0,
+ (dpcd_addr >> 16) & 0xf);
+
+ if (length > 0) {
+ DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0);
+ for (i = 0; i < (length + 1) / 2; i++)
+ for (reg_idx = 0; reg_idx < 2; reg_idx++)
+ if ((i * 2 + reg_idx) < length)
+ DP_WRITE1BYTE(mtk_dp,
+ REG_3708_AUX_TX_P0 + i * 4 + reg_idx,
+ data[i * 2 + reg_idx]);
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1,
+ ((length - 1) & 0xf) << 4);
+ } else {
+ DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x1);
+ }
+
+ mtk_dp_write_byte(mtk_dp, REG_3704_AUX_TX_P0,
+ AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK,
+ AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK);
+ DP_WRITE1BYTE(mtk_dp, REG_3630_AUX_TX_P0, 0x8);
+
+ while (--wait_reply_count) {
+ u8 aux_irq_status;
+
+ aux_irq_status = mtk_dp_read(mtk_dp, REG_3640_AUX_TX_P0) & 0xff;
+ mdelay(1);
+ if (aux_irq_status & AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK) {
+ valid_cmd = true;
+ break;
+ }
+
+ if (aux_irq_status & AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK)
+ break;
+ }
+
+ reply_cmd = mtk_dp_read(mtk_dp, REG_3624_AUX_TX_P0) & 0xf;
+ if (reply_cmd)
+ printk(BIOS_ERR, "reply_cmd(%#x), NACK or Defer\n", reply_cmd);
+
+ if (wait_reply_count == 0x0 || reply_cmd) {
+ u8 phy_status = 0x0;
+
+ phy_status = mtk_dp_read(mtk_dp, REG_3628_AUX_TX_P0);
+ if (phy_status != 0x1)
+ printk(BIOS_ERR,
+ "Aux write: aux hang, need SW reset!\n");
+
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1);
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+
+ mdelay(1);
+
+ printk(BIOS_INFO, "reply_cmd(%#x), wait_reply_count(%d)\n",
+ reply_cmd, wait_reply_count);
+ return false;
+ }
+
+ DP_WRITE1BYTE(mtk_dp, REG_3650_AUX_TX_P0 + 1, 0x1);
+
+ if (length == 0)
+ DP_WRITE1BYTE(mtk_dp, REG_362C_AUX_TX_P0, 0x0);
+
+ DP_WRITE1BYTE(mtk_dp, REG_3640_AUX_TX_P0, 0x7f);
+
+ mdelay(1);
+
+ return valid_cmd;
+}
+
+bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
+ int swing_value, int preemphasis)
+{
+ printk(BIOS_DEBUG, "lane(%d), set swing(%#x), emp(%#x)\n",
+ lane_num, swing_value, preemphasis);
+
+ if (lane_num >= DPTX_LANE_MAX) {
+ printk(BIOS_ERR, "invalid lane number: %d\n", lane_num);
+ return false;
+ }
+
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+ swing_value << volt_swing[lane_num].shift,
+ volt_swing[lane_num].mask);
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+ preemphasis << volt_preemphasis[lane_num].shift,
+ volt_preemphasis[lane_num].mask);
+ return true;
+}
+
+void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp)
+{
+ int lane;
+
+ for (lane = 0; lane < DPTX_LANE_MAX; lane++)
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+ 0, volt_swing[lane].mask);
+ for (lane = 0; lane < DPTX_LANE_MAX; lane++)
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_SWING_EMP,
+ 0, volt_preemphasis[lane].mask);
+}
+
+void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable)
+{
+ /* [7]:int, [6]:Con, [5]DisCon, [4]No-Use: UnMASK HPD Port */
+ mtk_dp_write_byte(mtk_dp, REG_3418_DP_TRANS_P0,
+ enable ? 0 : MASKBIT(7, 5), MASKBIT(7, 5));
+}
+
+void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0,
+ 0x8, MASKBIT(3, 0));
+ mtk_dp_write_byte(mtk_dp, REG_3410_DP_TRANS_P0,
+ 0xa << 4, MASKBIT(7, 4));
+
+ DP_WRITE1BYTE(mtk_dp, REG_3410_DP_TRANS_P0 + 1, 0x55);
+ DP_WRITE1BYTE(mtk_dp, REG_3430_DP_TRANS_P0, 0x2);
+}
+
+void dptx_hal_phy_setting(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_mask(mtk_dp, DP_TX_TOP_PWR_STATE,
+ 0x3 << DP_PWR_STATE_FLDMASK_POS, DP_PWR_STATE_FLDMASK);
+
+ mtk_dp_write(mtk_dp, 0x2000, 0x00000001);
+ mtk_dp_write(mtk_dp, 0x103c, 0x00000000);
+ mtk_dp_write(mtk_dp, 0x2000, 0x00000003);
+ mtk_dp_write(mtk_dp, 0x1138, 0x20181410);
+ mtk_dp_write(mtk_dp, 0x1238, 0x20181410);
+ mtk_dp_write(mtk_dp, 0x1338, 0x20181410);
+ mtk_dp_write(mtk_dp, 0x1438, 0x20181410);
+ mtk_dp_write(mtk_dp, 0x113C, 0x20241e18);
+ mtk_dp_write(mtk_dp, 0x123C, 0x20241e18);
+ mtk_dp_write(mtk_dp, 0x133C, 0x20241e18);
+ mtk_dp_write(mtk_dp, 0x143C, 0x20241e18);
+ mtk_dp_write(mtk_dp, 0x1140, 0x00003028);
+ mtk_dp_write(mtk_dp, 0x1240, 0x00003028);
+ mtk_dp_write(mtk_dp, 0x1340, 0x00003028);
+ mtk_dp_write(mtk_dp, 0x1440, 0x00003028);
+ mtk_dp_write(mtk_dp, 0x1144, 0x10080400);
+ mtk_dp_write(mtk_dp, 0x1244, 0x10080400);
+ mtk_dp_write(mtk_dp, 0x1344, 0x10080400);
+ mtk_dp_write(mtk_dp, 0x1444, 0x10080400);
+ mtk_dp_write(mtk_dp, 0x1148, 0x000c0600);
+ mtk_dp_write(mtk_dp, 0x1248, 0x000c0600);
+ mtk_dp_write(mtk_dp, 0x1348, 0x000c0600);
+ mtk_dp_write(mtk_dp, 0x1448, 0x000c0600);
+ mtk_dp_write(mtk_dp, 0x114C, 0x00000008);
+ mtk_dp_write(mtk_dp, 0x124C, 0x00000008);
+ mtk_dp_write(mtk_dp, 0x134C, 0x00000008);
+ mtk_dp_write(mtk_dp, 0x144C, 0x00000008);
+ mtk_dp_mask(mtk_dp, 0x3690, BIT(8), BIT(8));
+}
+
+void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_mask(mtk_dp, 0x2000, BIT(0), MASKBIT(1, 0));
+
+ if (enable)
+ mtk_dp_mask(mtk_dp, 0x1014, BIT(3), BIT(3));
+ else
+ mtk_dp_mask(mtk_dp, 0x1014, 0x0, BIT(3));
+
+ mtk_dp_mask(mtk_dp, 0x2000, MASKBIT(1, 0), MASKBIT(1, 0));
+
+ mdelay(1);
+}
+
+void dptx_hal_aux_setting(struct mtk_dp *mtk_dp)
+{
+ /* [12 : 8]: modify timeout threshold = 1595 */
+ mtk_dp_mask(mtk_dp, REG_360C_AUX_TX_P0,
+ 0x1595, AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK);
+ mtk_dp_write_byte(mtk_dp, REG_3658_AUX_TX_P0, 0, BIT(0));
+
+ /* 0x19 for 26M */
+ DP_WRITE1BYTE(mtk_dp, REG_3634_AUX_TX_P0 + 1, 0x19);
+ /* 0xd for 26M */
+ mtk_dp_write_byte(mtk_dp, REG_3614_AUX_TX_P0,
+ 0xd, MASKBIT(6, 0));
+ mtk_dp_mask(mtk_dp, REG_37C8_AUX_TX_P0,
+ 0x01 << MTK_ATOP_EN_AUX_TX_P0_FLDMASK_POS,
+ MTK_ATOP_EN_AUX_TX_P0_FLDMASK);
+}
+
+void dptx_hal_digital_setting(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write_byte(mtk_dp, REG_304C_DP_ENCODER0_P0,
+ 0, VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK);
+ /* MISC0 */
+ dptx_hal_set_color_format(mtk_dp, DP_COLOR_FORMAT_RGB_444);
+
+ dptx_hal_set_color_depth(mtk_dp, DP_COLOR_DEPTH_8BIT);
+ mtk_dp_write_byte(mtk_dp, REG_3368_DP_ENCODER1_P0 + 1,
+ BIT(4), MASKBIT(5, 4));
+ /* DPtx encoder reset all sw. */
+ mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, BIT(1), BIT(1));
+
+ mdelay(1);
+
+ /* DPtx encoder reset all sw. */
+ mtk_dp_write_byte(mtk_dp, REG_3004_DP_ENCODER0_P0 + 1, 0, BIT(1));
+}
+
+void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write_byte(mtk_dp, REG_340C_DP_TRANS_P0 + 1, BIT(5), BIT(5));
+ mdelay(1);
+ mtk_dp_write_byte(mtk_dp, REG_340C_DP_TRANS_P0 + 1, 0, BIT(5));
+}
+
+void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_write_byte(mtk_dp, 0x1038, 0, BIT(0));
+ mdelay(1);
+ mtk_dp_write_byte(mtk_dp, 0x1038, BIT(0), BIT(0));
+}
+
+void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, int value)
+{
+ if (value == 0)
+ mtk_dp_write_byte(mtk_dp, REG_35F0_DP_TRANS_P0,
+ 0, BIT(3) | BIT(2));
+ else
+ mtk_dp_write_byte(mtk_dp, REG_35F0_DP_TRANS_P0,
+ BIT(3), BIT(3) | BIT(2));
+
+ if ((value << 2) <= UINT8_MAX) {
+ mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0,
+ value, BIT(1) | BIT(0));
+ mtk_dp_write_byte(mtk_dp, REG_34A4_DP_TRANS_P0,
+ value << 2, BIT(3) | BIT(2));
+ } else {
+ printk(BIOS_ERR, "ERROR: [%s]value << 2 > 0xff\n", __func__);
+ }
+}
+
+void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value)
+{
+ /* Power off TPLL and lane */
+ mtk_dp_write(mtk_dp, 0x2000, 0x00000001);
+ /* Set gear : 0x0 : RBR, 0x1 : HBR, 0x2 : HBR2, 0x3 : HBR3 */
+ switch (value) {
+ case DP_LINKRATE_RBR:
+ mtk_dp_write(mtk_dp, 0x103C, 0x0);
+ break;
+ case DP_LINKRATE_HBR:
+ mtk_dp_write(mtk_dp, 0x103C, 0x1);
+ break;
+ case DP_LINKRATE_HBR2:
+ mtk_dp_write(mtk_dp, 0x103C, 0x2);
+ break;
+ case DP_LINKRATE_HBR3:
+ mtk_dp_write(mtk_dp, 0x103C, 0x3);
+ break;
+ default:
+ printk(BIOS_ERR, "ERROR: Link rate not support(%d)\n", value);
+ break;
+ }
+
+ /* Power on BandGap, TPLL and Lane */
+ mtk_dp_write(mtk_dp, 0x2000, 0x3);
+}
+
+void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value)
+{
+ /* if Set TPS1. */
+ if (value == BIT(4))
+ dptx_hal_phy_setidlepattern(mtk_dp, false);
+
+ mtk_dp_write_byte(mtk_dp, REG_3400_DP_TRANS_P0 + 1,
+ value, MASKBIT(7, 4));
+}
+
+void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable)
+{
+ mtk_dp_write_byte(mtk_dp, REG_3580_DP_TRANS_P0 + 1,
+ enable ? 0xf : 0x0, 0xf);
+}
+
+void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable)
+{
+ /*
+ * [4]: REG_enhanced_frame_mode
+ * [1 : 0]: REG_lane_num
+ */
+ if (enable)
+ mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0,
+ BIT(4), BIT(4));
+ else
+ mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0,
+ 0, BIT(4));
+}
+
+void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable)
+{
+ /* [0]: dp tx transmitter scramble enable. */
+ if (enable)
+ mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0,
+ BIT(0), BIT(0));
+ else
+ mtk_dp_write_byte(mtk_dp, REG_3404_DP_TRANS_P0,
+ 0, BIT(0));
+}
+
+void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable)
+{
+ if (enable) {
+ mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0,
+ BIT(3) | BIT(2), BIT(3) | BIT(2));
+ mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11,
+ BIT(3) | BIT(4), BIT(3) | BIT(4));
+ } else {
+ mtk_dp_write_byte(mtk_dp, REG_3000_DP_ENCODER0_P0,
+ BIT(3), BIT(3) | BIT(2));
+ mtk_dp_write_byte(mtk_dp, DP_TX_SECURE_REG11,
+ BIT(4), BIT(3) | BIT(4));
+ }
+ printk(BIOS_DEBUG, "mute = %#x\n", read32(mtk_dp->regs + 0x402c));
+}
+
+void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable)
+{
+ if (enable) {
+ mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE,
+ 0, BIT(4));
+ mdelay(1);
+ mtk_dp_write_byte(mtk_dp, DP_TX_TOP_RESET_AND_PROBE,
+ BIT(4), BIT(4));
+ } else {
+ DP_WRITE2BYTE(mtk_dp, TOP_OFFSET, 0x0);
+ mdelay(1);
+ DP_WRITE2BYTE(mtk_dp, 0x0034, 0x4aa);
+ DP_WRITE2BYTE(mtk_dp, 0x1040, 0x0);
+ DP_WRITE2BYTE(mtk_dp, 0x0038, 0x555);
+ }
+}
diff --git a/src/soc/mediatek/mt8195/include/soc/dp_intf.h b/src/soc/mediatek/mt8195/include/soc/dp_intf.h
new file mode 100644
index 0000000..ee142bf
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dp_intf.h
@@ -0,0 +1,258 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_DP_INTF_H
+#define SOC_MEDIATEK_MT8195_DP_INTF_H
+
+#include <edid.h>
+
+#define DPINTF_EN 0x00
+#define EN BIT(0)
+
+#define DPINTF_RET 0x04
+#define RST BIT(0)
+#define RST_SEL BIT(16)
+
+#define DPINTF_INTEN 0x08
+#define INT_VSYNC_EN BIT(0)
+#define INT_VDE_EN BIT(1)
+#define INT_UNDERFLOW_EN BIT(2)
+#define INT_TARGET_LINE_EN BIT(3)
+
+#define DPINTF_INTSTA 0x0C
+#define INT_VSYNC_STA BIT(0)
+#define INT_VDE_STA BIT(1)
+#define INT_UNDERFLOW_STA BIT(2)
+#define INT_TARGET_LINE_STA BIT(3)
+
+#define DPINTF_CON 0x10
+#define BG_ENABLE BIT(0)
+#define INTL_EN BIT(2)
+#define TDFP_EN BIT(3)
+#define VS_LODD_EN BIT(16)
+#define VS_LEVEN_EN BIT(17)
+#define VS_RODD_EN BIT(18)
+#define VS_REVEN BIT(19)
+#define FAKE_DE_LODD BIT(20)
+#define FAKE_DE_LEVEN BIT(21)
+#define FAKE_DE_RODD BIT(22)
+#define FAKE_DE_REVEN BIT(23)
+#define YUV422_EN BIT(24)
+#define CLPF_EN BIT(25)
+#define MATRIX_EN BIT(26)
+#define INTERNAL_CG_EN BIT(27)
+#define LOWPOWER_EN BIT(28)
+#define INPUT_2P_EN BIT(29)
+#define EXT_VSYNC_EN BIT(30)
+
+#define DPINTF_OUTPUT_SETTING 0x14
+#define PIXEL_SWAP BIT(0)
+#define CH_SWAP BIT(1)
+#define CH_SWAP_MASK (0x7 << 1)
+#define SWAP_RGB (0x00 << 1)
+#define SWAP_GBR (0x01 << 1)
+#define SWAP_BRG (0x02 << 1)
+#define SWAP_RBG (0x03 << 1)
+#define SWAP_GRB (0x04 << 1)
+#define SWAP_BGR (0x05 << 1)
+#define B_MASK BIT(4)
+#define G_MASK BIT(5)
+#define R_MASK BIT(6)
+#define DE_MASK BIT(8)
+#define HS_MASK BIT(9)
+#define VS_MASK BIT(10)
+#define HSYNC_POL BIT(13)
+#define VSYNC_POL BIT(14)
+#define OUT_BIT BIT(16)
+#define OUT_BIT_MASK (0x3 << 18)
+#define OUT_BIT_8 (0x00 << 18)
+#define OUT_BIT_10 (0x01 << 18)
+#define OUT_BIT_12 (0x02 << 18)
+#define OUT_BIT_16 (0x03 << 18)
+
+#define DPINTF_SIZE 0x18
+#define HSIZE 0
+#define HSIZE_MASK (0xffff << 0)
+#define VSIZE 16
+#define VSIZE_MASK (0xffff << 16)
+
+#define DPINTF_TGEN_HWIDTH 0x20
+#define HPW 0
+#define HPW_MASK (0xffff << 0)
+
+#define DPINTF_TGEN_HPORCH 0x24
+#define HBP 0
+#define HBP_MASK (0xffff << 0)
+#define HFP 16
+#define HFP_MASK (0xffff << 16)
+
+#define DPINTF_TGEN_VWIDTH 0x28
+#define VSYNC_WIDTH_SHIFT 0
+#define VSYNC_WIDTH_MASK (0xffff << 0)
+#define VSYNC_HALF_LINE_SHIFT 16
+#define VSYNC_HALF_LINE_MASK BIT(16)
+
+
+#define DPINTF_TGEN_VPORCH 0x2C
+#define VSYNC_BACK_PORCH_SHIFT 0
+#define VSYNC_BACK_PORCH_MASK (0xffff << 0)
+#define VSYNC_FRONT_PORCH_SHIFT 16
+#define VSYNC_FRONT_PORCH_MASK (0xffff << 16)
+
+#define DPINTF_BG_HCNTL 0x30
+#define BG_RIGHT (0xffff << 0)
+#define BG_LEFT (0xffff << 16)
+
+#define DPINTF_BG_VCNTL 0x34
+#define BG_BOT (0xffff << 0)
+#define BG_TOP (0xffff << 16)
+
+#define DPINTF_BG_COLOR 0x38
+#define BG_B (0x3ff << 0)
+#define BG_G (0x3ff << 10)
+#define BG_R (0x3ff << 20)
+
+#define DPINTF_FIFO_CTL 0x3C
+#define FIFO_VALID_SET (0x1F << 0)
+#define FIFO_RST_SEL BIT(8)
+#define FIFO_RD_MASK BIT(12)
+
+#define DPINTF_STATUS 0x40
+#define VCOUNTER (0x3ffff << 0)
+#define DPINTF_BUSY BIT(24)
+#define FIELD BIT(28)
+#define TDLR BIT(29)
+
+#define DPINTF_TGEN_VWIDTH_LEVEN 0x68
+#define DPINTF_TGEN_VPORCH_LEVEN 0x6C
+#define DPINTF_TGEN_VWIDTH_RODD 0x70
+#define DPINTF_TGEN_VPORCH_RODD 0x74
+#define DPINTF_TGEN_VWIDTH_REVEN 0x78
+#define DPINTF_TGEN_VPORCH_REVEN 0x7C
+
+#define DPINTF_CLPF_SETTING 0x94
+#define CLPF_TYPE (0x3 << 0)
+#define ROUND_EN BIT(4)
+
+#define DPINTF_Y_LIMIT 0x98
+#define Y_LIMINT_BOT 0
+#define Y_LIMINT_BOT_MASK (0xFFF << 0)
+#define Y_LIMINT_TOP 16
+#define Y_LIMINT_TOP_MASK (0xFFF << 16)
+
+#define DPINTF_C_LIMIT 0x9C
+#define C_LIMIT_BOT 0
+#define C_LIMIT_BOT_MASK (0xFFF << 0)
+#define C_LIMIT_TOP 16
+#define C_LIMIT_TOP_MASK (0xFFF << 16)
+
+#define DPINTF_YUV422_SETTING 0xA0
+#define UV_SWAP BIT(0)
+#define CR_DELSEL BIT(4)
+#define CB_DELSEL BIT(5)
+#define Y_DELSEL BIT(6)
+#define DE_DELSEL BIT(7)
+
+#define DPINTF_MATRIX_SET 0xB4
+#define INT_MATRIX_SEL_MASK 0x1f
+#define RGB_TO_JPEG 0x00
+#define RGB_TO_FULL709 0x01
+#define RGB_TO_BT601 0x02
+#define RGB_TO_BT709 0x03
+#define JPEG_TO_RGB 0x04
+#define FULL709_TO_RGB 0x05
+#define BT601_TO_RGB 0x06
+#define BT709_TO_RGB 0x07
+#define JPEG_TO_BT601 0x08
+#define JPEG_TO_BT709 0x09
+#define BT601_TO_JPEG 0xA
+#define BT709_TO_JPEG 0xB
+#define BT709_TO_BT601 0xC
+#define BT601_TO_BT709 0xD
+#define JPEG_TO_CERGB 0x14
+#define FULL709_TO_CERGB 0x15
+#define BT601_TO_CERGB 0x16
+#define BT709_TO_CERGB 0x17
+#define RGB_TO_CERGB 0x1C
+
+#define MATRIX_BIT_MASK (0x3 << 8)
+#define EXT_MATRIX_EN BIT(12)
+
+enum mtk_dpintf_out_bit_num {
+ MTK_DPINTF_OUT_BIT_NUM_8BITS,
+ MTK_DPINTF_OUT_BIT_NUM_10BITS,
+ MTK_DPINTF_OUT_BIT_NUM_12BITS,
+ MTK_DPINTF_OUT_BIT_NUM_16BITS,
+};
+
+enum mtk_dpintf_out_yc_map {
+ MTK_DPINTF_OUT_YC_MAP_RGB,
+ MTK_DPINTF_OUT_YC_MAP_CYCY,
+ MTK_DPINTF_OUT_YC_MAP_YCYC,
+ MTK_DPINTF_OUT_YC_MAP_CY,
+ MTK_DPINTF_OUT_YC_MAP_YC,
+};
+
+enum mtk_dpintf_out_channel_swap {
+ MTK_DPINTF_OUT_CHANNEL_SWAP_RGB,
+ MTK_DPINTF_OUT_CHANNEL_SWAP_GBR,
+ MTK_DPINTF_OUT_CHANNEL_SWAP_BRG,
+ MTK_DPINTF_OUT_CHANNEL_SWAP_RBG,
+ MTK_DPINTF_OUT_CHANNEL_SWAP_GRB,
+ MTK_DPINTF_OUT_CHANNEL_SWAP_BGR,
+};
+
+enum mtk_dpintf_out_color_format {
+ MTK_DPINTF_COLOR_FORMAT_RGB,
+ MTK_DPINTF_COLOR_FORMAT_RGB_FULL,
+ MTK_DPINTF_COLOR_FORMAT_YCBCR_444,
+ MTK_DPINTF_COLOR_FORMAT_YCBCR_422,
+ MTK_DPINTF_COLOR_FORMAT_XV_YCC,
+ MTK_DPINTF_COLOR_FORMAT_YCBCR_444_FULL,
+ MTK_DPINTF_COLOR_FORMAT_YCBCR_422_FULL,
+};
+
+enum TVDPLL_CLK {
+ TVDPLL_PLL = 0,
+ TVDPLL_D2 = 1,
+ TVDPLL_D4 = 3,
+ TVDPLL_D8 = 5,
+ TVDPLL_D16 = 7,
+};
+
+struct mtk_dpintf {
+ void *regs;
+ enum mtk_dpintf_out_color_format color_format;
+ enum mtk_dpintf_out_yc_map yc_map;
+ enum mtk_dpintf_out_bit_num bit_num;
+ enum mtk_dpintf_out_channel_swap channel_swap;
+};
+
+enum mtk_dpintf_polarity {
+ MTK_DPINTF_POLARITY_RISING,
+ MTK_DPINTF_POLARITY_FALLING,
+};
+
+struct mtk_dpintf_polarities {
+ enum mtk_dpintf_polarity de_pol;
+ enum mtk_dpintf_polarity ck_pol;
+ enum mtk_dpintf_polarity hsync_pol;
+ enum mtk_dpintf_polarity vsync_pol;
+};
+
+struct mtk_dpintf_sync_param {
+ u32 sync_width;
+ u32 front_porch;
+ u32 back_porch;
+ bool shift_half_line;
+};
+
+struct mtk_dpintf_yc_limit {
+ u16 y_top;
+ u16 y_bottom;
+ u16 c_top;
+ u16 c_bottom;
+};
+
+void dp_intf_config(const struct edid *edid);
+
+#endif /* SOC_MEDIATEK_MT8195_DP_INTF_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/dptx.h b/src/soc/mediatek/mt8195/include/soc/dptx.h
new file mode 100644
index 0000000..54b28ec
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dptx.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_DPTX_H
+#define SOC_MEDIATEK_MT8195_DPTX_H
+
+#define DPTX_TBC_BUF_READSTARTADRTHRD 0x08
+#define ENABLE_DPTX_EF_MODE 0x1
+#define DPTX_AUX_SET_ENAHNCED_FRAME 0x80
+
+union misc_t {
+ struct {
+ u8 is_sync_clock : 1;
+ u8 color_format : 2;
+ u8 spec_def1 : 2;
+ u8 color_depth : 3;
+ u8 interlaced : 1;
+ u8 stereo_attr : 2;
+ u8 reserved : 3;
+ u8 is_vsc_sdp : 1;
+ u8 spec_def2 : 1;
+ } dp_misc;
+ u8 cmisc[2];
+};
+
+struct dptx_training_info {
+ bool sink_extcap_en;
+ bool tps3;
+ bool tps4;
+ bool sink_ssc_en;
+ bool dp_mstcap;
+ bool dp_mstbranch;
+ bool down_stream_port_present;
+ bool cr_done;
+ bool eq_done;
+ u8 sys_max_linkrate;
+ u8 linkrate;
+ u8 linklane_count;
+ u8 dpcd_rev;
+ u8 sink_count_num;
+};
+
+struct dptx_info {
+ uint8_t depth;
+ uint8_t format;
+ uint8_t resolution;
+};
+
+struct mtk_dp {
+ int id;
+ struct edid *edid;
+ u8 rx_cap[16];
+ struct dptx_info info;
+ int state;
+ int state_pre;
+ struct dptx_training_info train_info;
+ int training_state;
+ u8 irq_status;
+ u32 min_clock;
+ u32 max_clock;
+ u32 max_hdisplay;
+ u32 max_vdisplay;
+ void *regs;
+ int disp_status;
+ bool power_on;
+ bool audio_enable;
+ bool video_enable;
+ bool dp_ready;
+ bool has_dsc;
+ bool has_fec;
+ bool dsc_enable;
+ bool enabled;
+ bool powered;
+};
+
+int mtk_edp_init(struct edid *edid);
+
+#endif /* SOC_MEDIATEK_MT8195_DPTX_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_hal.h b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h
new file mode 100644
index 0000000..b943c27
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dptx_hal.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_DPTX_HAL_H
+#define SOC_MEDIATEK_MT8195_DPTX_HAL_H
+
+#define AUX_CMD_I2C_R_MOT0 0x1
+#define AUX_CMD_I2C_R 0x5
+#define AUX_CMD_NATIVE_R 0x9
+#define AUX_WAITREPLY_LPNUM 20000
+
+#define DP_AUX_I2C_WRITE 0x0
+#define DP_AUX_I2C_READ 0x1
+#define DP_AUX_I2C_WRITE_STATUS_UPDATE 0x2
+#define DP_AUX_I2C_MOT 0x4
+#define DP_AUX_NATIVE_WRITE 0x8
+#define DP_AUX_NATIVE_READ 0x9
+
+#define MASKBIT(a, b) ((a > b) ? (BIT(a + 1) - BIT(b)) : (BIT(b + 1) - BIT(a)))
+
+#define DP_WRITE1BYTE(mtk_dp, reg, u8_val) \
+ mtk_dp_write_byte(mtk_dp, reg, u8_val, 0xff)
+#define DP_WRITE2BYTE(mtk_dp, reg, u16_val) \
+ mtk_dp_mask(mtk_dp, reg, u16_val, 0xffff)
+
+enum {
+ DPTX_LANE0 = 0x0,
+ DPTX_LANE1 = 0x1,
+ DPTX_LANE2 = 0x2,
+ DPTX_LANE3 = 0x3,
+ DPTX_LANE_MAX,
+};
+
+enum {
+ DP_LINKRATE_RBR = 0x6,
+ DP_LINKRATE_HBR = 0xa,
+ DP_LINKRATE_HBR2 = 0x14,
+ DP_LINKRATE_HBR25 = 0x19,
+ DP_LINKRATE_HBR3 = 0x1e,
+};
+
+enum {
+ DP_COLOR_FORMAT_RGB_444 = 0,
+ DP_COLOR_FORMAT_YUV_422 = 1,
+ DP_COLOR_FORMAT_YUV_444 = 2,
+ DP_COLOR_FORMAT_YUV_420 = 3,
+ DP_COLOR_FORMAT_YONLY = 4,
+ DP_COLOR_FORMAT_RAW = 5,
+ DP_COLOR_FORMAT_RESERVED = 6,
+ DP_COLOR_FORMAT_DEFAULT = DP_COLOR_FORMAT_RGB_444,
+ DP_COLOR_FORMAT_UNKNOWN = 15,
+};
+
+enum {
+ DP_COLOR_DEPTH_6BIT = 0,
+ DP_COLOR_DEPTH_8BIT = 1,
+ DP_COLOR_DEPTH_10BIT = 2,
+ DP_COLOR_DEPTH_12BIT = 3,
+ DP_COLOR_DEPTH_16BIT = 4,
+ DP_COLOR_DEPTH_UNKNOWN = 5,
+};
+
+bool dptx_hal_hpd_high(struct mtk_dp *mtk_dp);
+bool dptx_hal_auxread_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *rx_buf);
+bool dptx_hal_auxwrite_bytes(struct mtk_dp *mtk_dp, u8 cmd,
+ u32 dpcd_addr, size_t length, u8 *data);
+bool dptx_hal_setswing_preemphasis(struct mtk_dp *mtk_dp, int lane_num,
+ int swing_value, int preemphasis);
+u8 dptx_hal_get_colorbpp(struct mtk_dp *mtk_dp);
+u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset);
+void mtk_dp_write_byte(struct mtk_dp *mtk_dp, u32 addr, u8 val, u32 mask);
+void mtk_dp_mask(struct mtk_dp *mtk_dp, u32 offset, u32 val, u32 mask);
+void mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val);
+void dptx_hal_verify_clock(struct mtk_dp *mtk_dp);
+void dptx_hal_reset_swing_preemphasis(struct mtk_dp *mtk_dp);
+void dptx_hal_digital_swreset(struct mtk_dp *mtk_dp);
+void dptx_hal_ssc_en(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_hpd_int_en(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_hpd_detect_setting(struct mtk_dp *mtk_dp);
+void dptx_hal_phy_setting(struct mtk_dp *mtk_dp);
+void dptx_hal_aux_setting(struct mtk_dp *mtk_dp);
+void dptx_hal_digital_setting(struct mtk_dp *mtk_dp);
+void dptx_hal_set_txlane(struct mtk_dp *mtk_dp, int value);
+void dptx_hal_phy_setidlepattern(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_phyd_reset(struct mtk_dp *mtk_dp);
+void dptx_hal_set_txtrainingpattern(struct mtk_dp *mtk_dp, int value);
+void dptx_hal_set_ef_mode(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_setscramble(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_init_setting(struct mtk_dp *mtk_dp);
+void dptx_hal_videomute(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_bypassmsa_en(struct mtk_dp *mtk_dp, bool enable);
+void dptx_hal_overwrite_mn(struct mtk_dp *mtk_dp, bool enable,
+ u32 video_m, u32 video_n);
+void dptx_hal_settu_sramrd_start(struct mtk_dp *mtk_dp, u16 value);
+void dptx_hal_setsdp_downcnt_init_inhblanking(struct mtk_dp *mtk_dp, u16 value);
+void dptx_hal_setsdp_downcnt_init(struct mtk_dp *mtk_dp, u16 value);
+void dptx_hal_settu_setencoder(struct mtk_dp *mtk_dp);
+void dptx_hal_set_msa(struct mtk_dp *mtk_dp);
+void dptx_hal_setmisc(struct mtk_dp *mtk_dp, u8 cmisc[2]);
+void dptx_hal_set_color_depth(struct mtk_dp *mtk_dp, u8 color_depth);
+void dptx_hal_set_color_format(struct mtk_dp *mtk_dp, u8 color_format);
+void dptx_hal_set_txrate(struct mtk_dp *mtk_dp, int value);
+void dptx_hal_analog_power_en(struct mtk_dp *mtk_dp, bool enable);
+
+#endif /* SOC_MEDIATEK_MT8195_DPTX_HAL_H */
diff --git a/src/soc/mediatek/mt8195/include/soc/dptx_reg.h b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h
new file mode 100644
index 0000000..a010517
--- /dev/null
+++ b/src/soc/mediatek/mt8195/include/soc/dptx_reg.h
@@ -0,0 +1,4740 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SOC_MEDIATEK_MT8195_DRTX_REG_H
+#define SOC_MEDIATEK_MT8195_DRTX_REG_H
+
+#define TOP_OFFSET 0x2000
+#define ENC0_OFFSET 0x3000
+#define ENC1_OFFSET 0x3200
+#define TRANS_OFFSET 0x3400
+#define AUX_OFFSET 0x3600
+#define SEC_OFFSET 0x4000
+
+#define REG_3000_DP_ENCODER0_P0 0x3000
+#define LANE_NUM_DP_ENCODER0_P0_FLDMASK 0x3
+#define LANE_NUM_DP_ENCODER0_P0_FLDMASK_POS 0
+#define LANE_NUM_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK 0x4
+#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_POS 2
+#define VIDEO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK 0x8
+#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_POS 3
+#define VIDEO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK 0x10
+#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK_POS 4
+#define ENHANCED_FRAME_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK 0x20
+#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK_POS 5
+#define HDCP_FRAME_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define IDP_EN_DP_ENCODER0_P0_FLDMASK 0x40
+#define IDP_EN_DP_ENCODER0_P0_FLDMASK_POS 6
+#define IDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK 0x80
+#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK_POS 7
+#define BS_SYMBOL_CNT_RESET_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK 0xff00
+#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_POS 8
+#define MIXER_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3004_DP_ENCODER0_P0 0x3004
+#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK 0xff
+#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_POS 0
+#define MIXER_STUFF_DUMMY_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK 0x100
+#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VIDEO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x200
+#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 9
+#define DP_TX_ENCODER_4P_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x400
+#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 10
+#define MIXER_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x800
+#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 11
+#define VIDEO_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x1000
+#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 12
+#define VIDEO_PATTERN_GEN_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK 0x2000
+#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK_POS 13
+#define SDP_RESET_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK 0x4000
+#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK_POS 14
+#define DP_TX_MUX_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK 0x8000
+#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK_POS 15
+#define MIXER_FSM_RESET_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3008_DP_ENCODER0_P0 0x3008
+#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_300C_DP_ENCODER0_P0 0x300C
+#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK 0x100
+#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VIDEO_M_CODE_PULSE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK 0x200
+#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK_POS 9
+#define COMPRESSEDSTREAM_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK 0x400
+#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK_POS 10
+#define SDP_SPLIT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK 0x800
+#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK_POS 11
+#define SDP_SPLIT_FIFO_RST_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK 0x7000
+#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_POS 12
+#define VIDEO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK 0x8000
+#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK_POS 15
+#define SDP_AUDIO_ONE_SAMPLE_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3010_DP_ENCODER0_P0 0x3010
+#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK_PO 0
+#define HTOTAL_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3014_DP_ENCODER0_P0 0x3014
+#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VTOTAL_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3018_DP_ENCODER0_P0 0x3018
+#define HSTART_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define HSTART_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HSTART_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_301C_DP_ENCODER0_P0 0x301C
+#define VSTART_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VSTART_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSTART_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3020_DP_ENCODER0_P0 0x3020
+#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HWIDTH_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3024_DP_ENCODER0_P0 0x3024
+#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VHEIGHT_SW_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3028_DP_ENCODER0_P0 0x3028
+#define HSW_SW_DP_ENCODER0_P0_FLDMASK 0x7fff
+#define HSW_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HSW_SW_DP_ENCODER0_P0_FLDMASK_LEN 15
+
+#define HSP_SW_DP_ENCODER0_P0_FLDMASK 0x8000
+#define HSP_SW_DP_ENCODER0_P0_FLDMASK_POS 15
+#define HSP_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_302C_DP_ENCODER0_P0 0x302C
+#define VSW_SW_DP_ENCODER0_P0_FLDMASK 0x7fff
+#define VSW_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSW_SW_DP_ENCODER0_P0_FLDMASK_LEN 15
+
+#define VSP_SW_DP_ENCODER0_P0_FLDMASK 0x8000
+#define VSP_SW_DP_ENCODER0_P0_FLDMASK_POS 15
+#define VSP_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3030_DP_ENCODER0_P0 0x3030
+#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK 0x1
+#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK 0x2
+#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_POS 1
+#define VTOTAL_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK 0x4
+#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK_POS 2
+#define HSTART_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK 0x8
+#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK_POS 3
+#define VSTART_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK 0x10
+#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
+#define HWIDTH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK 0x20
+#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK_POS 5
+#define VHEIGHT_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HSP_SEL_DP_ENCODER0_P0_FLDMASK 0x40
+#define HSP_SEL_DP_ENCODER0_P0_FLDMASK_POS 6
+#define HSP_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HSW_SEL_DP_ENCODER0_P0_FLDMASK 0x80
+#define HSW_SEL_DP_ENCODER0_P0_FLDMASK_POS 7
+#define HSW_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VSP_SEL_DP_ENCODER0_P0_FLDMASK 0x100
+#define VSP_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSP_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VSW_SEL_DP_ENCODER0_P0_FLDMASK 0x200
+#define VSW_SEL_DP_ENCODER0_P0_FLDMASK_POS 9
+#define VSW_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK 0x400
+#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_POS 10
+#define TX_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENCODER0_P0_FLDMASK 0x800
+#define VBID_AUDIO_MUTE_SW_DP_ENCODER0_P0_FLDMASK_POS 11
+#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK 0x1000
+#define VBID_AUDIO_MUTE_SEL_DP_ENCODER0_P0_FLDMASK_POS 12
+#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK 0x2000
+#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_POS 13
+#define VBID_INTERLACE_FLAG_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
+#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
+#define VBID_INTERLACE_FLAG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK 0x8000
+#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK_POS 15
+#define MIXER_SDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3034_DP_ENCODER0_P0 0x3034
+#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK 0xff
+#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK_POS 0
+#define MISC0_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK 0xff00
+#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK_POS 8
+#define MISC1_DATA_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3038_DP_ENCODER0_P0 0x3038
+#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK 0xff
+#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define TX_VBID_SW_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK 0x700
+#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VIDEO_DATA_SWAP_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK 0x800
+#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK_POS 11
+#define VIDEO_SOURCE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK 0x1000
+#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_POS 12
+#define FIELD_VBID_SW_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define FIELD_SW_DP_ENCODER0_P0_FLDMASK 0x2000
+#define FIELD_SW_DP_ENCODER0_P0_FLDMASK_POS 13
+#define FIELD_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK 0x4000
+#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK_POS 14
+#define V3D_EN_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK 0x8000
+#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK_POS 15
+#define V3D_LR_HW_SWAP_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_303C_DP_ENCODER0_P0 0x303C
+#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK 0x3f
+#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK_POS 0
+#define SRAM_START_READ_THRD_DP_ENCODER0_P0_FLDMASK_LEN 6
+
+#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK 0x700
+#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VIDEO_COLOR_DEPTH_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK 0x7000
+#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK_POS 12
+#define PIXEL_ENCODE_FORMAT_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x8000
+#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 15
+#define VIDEO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3040_DP_ENCODER0_P0 0x3040
+#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK 0xfff
+#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK_POS 0
+#define SDP_DOWN_CNT_INIT_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK 0x1000
+#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK_POS 12
+#define AUDIO_32CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK 0x2000
+#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 13
+#define AUDIO_32CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK 0x4000
+#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK_POS 14
+#define AUDIO_16CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
+#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
+#define AUDIO_16CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3044_DP_ENCODER0_P0 0x3044
+#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3048_DP_ENCODER0_P0 0x3048
+#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_304C_DP_ENCODER0_P0 0x304C
+#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK 0x3
+#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_SRAM_MODE_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK 0x4
+#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK_POS 2
+#define VBID_VIDEO_MUTE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK 0x8
+#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK_POS 3
+#define VBID_VIDEO_MUTE_IDLE_PATTERN_SYNC_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK 0x10
+#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
+#define HDCP_SYNC_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK 0x20
+#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK_POS 5
+#define HDCP_SYNC_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK 0x100
+#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK_POS 8
+#define SDP_VSYNC_RISING_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3050_DP_ENCODER0_P0 0x3050
+#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3054_DP_ENCODER0_P0 0x3054
+#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3058_DP_ENCODER0_P0 0x3058
+#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_N_CODE_MN_GEN_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_305C_DP_ENCODER0_P0 0x305C
+#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_N_CODE_MN_GEN_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3060_DP_ENCODER0_P0 0x3060
+#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK 0x7
+#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK_POS 0
+#define NUM_INTERLACE_FRAME_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK 0x8
+#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK_POS 3
+#define INTERLACE_DET_EVEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK 0x10
+#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK_POS 4
+#define FIELD_DETECT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK 0xff00
+#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK_POS 8
+#define FIELD_DETECT_UPDATE_THRD_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3064_DP_ENCODER0_P0 0x3064
+#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK 0xffff
+#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HDE_NUM_LAST_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3088_DP_ENCODER0_P0 0x3088
+#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK 0x20
+#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK_POS 5
+#define AUDIO_DETECT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AU_EN_DP_ENCODER0_P0_FLDMASK 0x40
+#define AU_EN_DP_ENCODER0_P0_FLDMASK_POS 6
+#define AU_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK 0x80
+#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK_POS 7
+#define AUDIO_8CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK 0x100
+#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AUDIO_8CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x200
+#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 9
+#define AU_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK 0x1000
+#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_POS 12
+#define AUDIO_MN_GEN_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define DIS_ASP_DP_ENCODER0_P0_FLDMASK 0x2000
+#define DIS_ASP_DP_ENCODER0_P0_FLDMASK_POS 13
+#define DIS_ASP_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK 0x4000
+#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK_POS 14
+#define AUDIO_2CH_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
+#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
+#define AUDIO_2CH_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_308C_DP_ENCODER0_P0 0x308C
+#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define CH_STATUS_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3090_DP_ENCODER0_P0 0x3090
+#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK 0xffff
+#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define CH_STATUS_1_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3094_DP_ENCODER0_P0 0x3094
+#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK 0xff
+#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define CH_STATUS_2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3098_DP_ENCODER0_P0 0x3098
+#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define USER_DATA_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_309C_DP_ENCODER0_P0 0x309C
+#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK 0xffff
+#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define USER_DATA_1_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_30A0_DP_ENCODER0_P0 0x30A0
+#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK 0xff
+#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define USER_DATA_2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK 0xf00
+#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_VESA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 4
+
+#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK 0xf000
+#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK_POS 12
+#define VSC_EXT_CEA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 4
+
+#define REG_30A4_DP_ENCODER0_P0 0x30A4
+#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AU_TS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AVI_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AVI_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AVI_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30A8_DP_ENCODER0_P0 0x30A8
+#define AUI_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUI_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUI_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define SPD_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define SPD_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define SPD_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30AC_DP_ENCODER0_P0 0x30AC
+#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define MPEG_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define NTSC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30B0_DP_ENCODER0_P0 0x30B0
+#define VSP_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSP_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSP_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define EXT_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define EXT_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define EXT_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30B4_DP_ENCODER0_P0 0x30B4
+#define ACM_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define ACM_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ACM_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ISRC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30B8_DP_ENCODER0_P0 0x30B8
+#define VSC_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define MSA_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define MSA_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define MSA_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30BC_DP_ENCODER0_P0 0x30BC
+#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK 0x1
+#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ISRC_CONT_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK 0x2
+#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK_POS 1
+#define MSA_BY_SDP_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_EN_DP_ENCODER0_P0_FLDMASK 0x4
+#define SDP_EN_DP_ENCODER0_P0_FLDMASK_POS 2
+#define SDP_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK 0x8
+#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK_POS 3
+#define NIBBLE_INTERLEAVER_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ECC_EN_DP_ENCODER0_P0_FLDMASK 0x10
+#define ECC_EN_DP_ENCODER0_P0_FLDMASK_POS 4
+#define ECC_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK 0x60
+#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK_POS 5
+#define ASP_MIN_PL_SIZE_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK 0x700
+#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
+#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
+#define AUDIO_M_CODE_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK 0x8000
+#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK_POS 15
+#define ASP_HB23_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_30C0_DP_ENCODER0_P0 0x30C0
+#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AU_TS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AU_TS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30C4_DP_ENCODER0_P0 0x30C4
+#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AU_TS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AU_TS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30C8_DP_ENCODER0_P0 0x30C8
+#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_M_CODE_SW_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_30CC_DP_ENCODER0_P0 0x30CC
+#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_M_CODE_SW_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30D0_DP_ENCODER0_P0 0x30D0
+#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_N_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_30D4_DP_ENCODER0_P0 0x30D4
+#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUDIO_N_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30D8_DP_ENCODER0_P0 0x30D8
+#define ACM_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define ACM_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ACM_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ACM_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ACM_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ACM_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30DC_DP_ENCODER0_P0 0x30DC
+#define ACM_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define ACM_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ACM_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ACM_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ACM_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ACM_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30E0_DP_ENCODER0_P0 0x30E0
+#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ISRC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ISRC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30E4_DP_ENCODER0_P0 0x30E4
+#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ISRC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ISRC0_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30E8_DP_ENCODER0_P0 0x30E8
+#define AVI_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define AVI_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AVI_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AVI_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AVI_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AVI_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30EC_DP_ENCODER0_P0 0x30EC
+#define AVI_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define AVI_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AVI_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AVI_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AVI_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AVI_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30F0_DP_ENCODER0_P0 0x30F0
+#define AUI_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUI_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUI_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AUI_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AUI_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AUI_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30F4_DP_ENCODER0_P0 0x30F4
+#define AUI_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define AUI_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define AUI_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define AUI_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define AUI_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define AUI_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30F8_DP_ENCODER0_P0 0x30F8
+#define SPD_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define SPD_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define SPD_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define SPD_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define SPD_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define SPD_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_30FC_DP_ENCODER0_P0 0x30FC
+#define SPD_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define SPD_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define SPD_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define SPD_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define SPD_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define SPD_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3100_DP_ENCODER0_P0 0x3100
+#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define MPEG_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define MPEG_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3104_DP_ENCODER0_P0 0x3104
+#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define MPEG_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define MPEG_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3108_DP_ENCODER0_P0 0x3108
+#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define NTSC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define NTSC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_310C_DP_ENCODER0_P0 0x310C
+#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define NTSC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define NTSC_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3110_DP_ENCODER0_P0 0x3110
+#define VSP_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSP_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSP_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSP_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSP_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSP_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3114_DP_ENCODER0_P0 0x3114
+#define VSP_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSP_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSP_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSP_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSP_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSP_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3118_DP_ENCODER0_P0 0x3118
+#define VSC_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_311C_DP_ENCODER0_P0 0x311C
+#define VSC_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3120_DP_ENCODER0_P0 0x3120
+#define EXT_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define EXT_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define EXT_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define EXT_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define EXT_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define EXT_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3124_DP_ENCODER0_P0 0x3124
+#define EXT_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define EXT_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define EXT_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define EXT_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define EXT_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define EXT_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3128_DP_ENCODER0_P0 0x3128
+#define ASP_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define ASP_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ASP_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ASP_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ASP_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ASP_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_312C_DP_ENCODER0_P0 0x312C
+#define ASP_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define ASP_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ASP_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ASP_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ASP_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ASP_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3130_DP_ENCODER0_P0 0x3130
+#define PPS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define PPS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PPS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define PPS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define PPS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define PPS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3134_DP_ENCODER0_P0 0x3134
+#define PPS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define PPS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PPS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define PPS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define PPS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define PPS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3138_DP_ENCODER0_P0 0x3138
+#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HDR0_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define HDR0_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_313C_DP_ENCODER0_P0 0x313C
+#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HDR0_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define HDR0_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_3140_DP_ENCODER0_P0 0x3140
+#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_CURSOR_V_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK 0x2000
+#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK_POS 13
+#define PGEN_TG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK 0x4000
+#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK_POS 14
+#define PGEN_PG_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK 0x8000
+#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK_POS 15
+#define PGEN_CURSOR_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3144_DP_ENCODER0_P0 0x3144
+#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_CURSOR_H_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_3148_DP_ENCODER0_P0 0x3148
+#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_CURSOR_RGB_COLOR_CODE_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_314C_DP_ENCODER0_P0 0x314C
+#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK 0xffff
+#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_CURSOR_RGB_COLOR_CODE_1_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_3150_DP_ENCODER0_P0 0x3150
+#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK 0xf
+#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_CURSOR_RGB_COLOR_CODE_2_DP_ENCODER0_P0_FLDMASK_LEN 4
+
+#define REG_3154_DP_ENCODER0_P0 0x3154
+#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_HTOTAL_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_3158_DP_ENCODER0_P0 0x3158
+#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_HSYNC_RISING_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_315C_DP_ENCODER0_P0 0x315C
+#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_HSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_3160_DP_ENCODER0_P0 0x3160
+#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_HFDE_START_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_3164_DP_ENCODER0_P0 0x3164
+#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_3168_DP_ENCODER0_P0 0x3168
+#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_VTOTAL_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_316C_DP_ENCODER0_P0 0x316C
+#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_VSYNC_RISING_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_3170_DP_ENCODER0_P0 0x3170
+#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_VSYNC_PULSE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_3174_DP_ENCODER0_P0 0x3174
+#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_VFDE_START_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_3178_DP_ENCODER0_P0 0x3178
+#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_317C_DP_ENCODER0_P0 0x317C
+#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_BASE_PIXEL_0_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_3180_DP_ENCODER0_P0 0x3180
+#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_BASE_PIXEL_1_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_3184_DP_ENCODER0_P0 0x3184
+#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_BASE_PIXEL_2_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_3188_DP_ENCODER0_P0 0x3188
+#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_INITIAL_H_CNT_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_318C_DP_ENCODER0_P0 0x318C
+#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_INITIAL_V_CNT_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_3190_DP_ENCODER0_P0 0x3190
+#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK 0x7
+#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_INITIAL_CB_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK 0x10
+#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK_POS 4
+#define PGEN_FRAME_8K4K_MODE_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK 0x20
+#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK_POS 5
+#define PGEN_FRAME_8K4K_MODE_SET_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK 0x40
+#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_POS 6
+#define PGEN_INITIAL_H_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK 0x80
+#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_POS 7
+#define PGEN_INITIAL_V_GRAD_FLAG_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK 0x100
+#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK_POS 8
+#define PGEN_FRAME_END_H_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK 0x200
+#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK_POS 9
+#define PGEN_FRAME_END_V_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3194_DP_ENCODER0_P0 0x3194
+#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_EXTRA_PIXEL_0_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_3198_DP_ENCODER0_P0 0x3198
+#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_EXTRA_PIXEL_1_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_319C_DP_ENCODER0_P0 0x319C
+#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK 0xfff
+#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_EXTRA_PIXEL_2_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_31A0_DP_ENCODER0_P0 0x31A0
+#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK 0xffff
+#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_INCREMENT_0_DP_ENCODER0_P0_FLDMASK_LEN 16
+
+#define REG_31A4_DP_ENCODER0_P0 0x31A4
+#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK 0x1
+#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_INCREMENT_1_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_31A8_DP_ENCODER0_P0 0x31A8
+#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK 0x3fff
+#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_HWIDTH_DP_ENCODER0_P0_FLDMASK_LEN 14
+
+#define REG_31AC_DP_ENCODER0_P0 0x31AC
+#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK 0x1fff
+#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_VWIDTH_DP_ENCODER0_P0_FLDMASK_LEN 13
+
+#define REG_31B0_DP_ENCODER0_P0 0x31B0
+#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK 0x7
+#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_RGB_ENABLE_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK 0x70
+#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
+#define PGEN_PATTERN_SEL_DP_ENCODER0_P0_FLDMASK_LEN 3
+
+#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK 0x80
+#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK_POS 7
+#define PGEN_PAT_DIRECTION_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK 0x100
+#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_POS 8
+#define PGEN_PAT_GRADIENT_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK 0x200
+#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK_POS 9
+#define PGEN_PAT_COLOR_BAR_GRADIENT_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK 0x400
+#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_POS 10
+#define PGEN_PAT_CHESSBOARD_NORMAL_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK 0x800
+#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK_POS 11
+#define PGEN_PAT_EXCHANGE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK 0x1000
+#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK_POS 12
+#define PGEN_PAT_RGB_SUB_PIXEL_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_31B4_DP_ENCODER0_P0 0x31B4
+#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK 0xf
+#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PGEN_PAT_THICKNESS_DP_ENCODER0_P0_FLDMASK_LEN 4
+
+#define REG_31C0_DP_ENCODER0_P0 0x31C0
+#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK 0xfff
+#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_MUTE_CNT_THRD_DP_ENCODER0_P0_FLDMASK_LEN 12
+
+#define REG_31C4_DP_ENCODER0_P0 0x31C4
+#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x800
+#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 11
+#define PPS_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MST_EN_DP_ENCODER0_P0_FLDMASK 0x1000
+#define MST_EN_DP_ENCODER0_P0_FLDMASK_POS 12
+#define MST_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK 0x2000
+#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK_POS 13
+#define DSC_BYPASS_EN_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x4000
+#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 14
+#define VSC_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK 0x8000
+#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_POS 15
+#define HDR0_HW_BYPASS_MASK_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_31C8_DP_ENCODER0_P0 0x31C8
+#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_EXT_VESA_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_VESA_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31CC_DP_ENCODER0_P0 0x31CC
+#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_EXT_VESA_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_VESA_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31D0_DP_ENCODER0_P0 0x31D0
+#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_EXT_CEA_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_CEA_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31D4_DP_ENCODER0_P0 0x31D4
+#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_EXT_CEA_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_CEA_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31D8_DP_ENCODER0_P0 0x31D8
+#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK 0x3f
+#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VSC_EXT_VESA_NUM_DP_ENCODER0_P0_FLDMASK_LEN 6
+
+#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK 0x3f00
+#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK_POS 8
+#define VSC_EXT_CEA_NUM_DP_ENCODER0_P0_FLDMASK_LEN 6
+
+#define REG_31DC_DP_ENCODER0_P0 0x31DC
+#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define HDR0_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK 0xff00
+#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK_POS 8
+#define RESERVED_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31E0_DP_ENCODER0_P0 0x31E0
+#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define RESERVED_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define RESERVED_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31E4_DP_ENCODER0_P0 0x31E4
+#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define RESERVED_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define RESERVED_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31E8_DP_ENCODER0_P0 0x31E8
+#define PPS_CFG_DP_ENCODER0_P0_FLDMASK 0xff
+#define PPS_CFG_DP_ENCODER0_P0_FLDMASK_POS 0
+#define PPS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK 0x100
+#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK_POS 8
+#define PPS_CFG_ONE_TIME_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK 0xf000
+#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK_POS 12
+#define SDP_SPLIT_FIFO_READ_START_POINT_DP_ENCODER0_P0_FLDMASK_LEN 4
+
+#define REG_31EC_DP_ENCODER0_P0 0x31EC
+#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK 0x1
+#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_M_CODE_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK 0x2
+#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_POS 1
+#define MSA_MISC_FROM_DPRX_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ADS_CFG_DP_ENCODER0_P0_FLDMASK 0x4
+#define ADS_CFG_DP_ENCODER0_P0_FLDMASK_POS 2
+#define ADS_CFG_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ADS_MODE_DP_ENCODER0_P0_FLDMASK 0x8
+#define ADS_MODE_DP_ENCODER0_P0_FLDMASK_POS 3
+#define ADS_MODE_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK 0x10
+#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK_POS 4
+#define AUDIO_CH_SRC_SEL_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ISRC1_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31F0_DP_ENCODER0_P0 0x31F0
+#define ADS_HB0_DP_ENCODER0_P0_FLDMASK 0xff
+#define ADS_HB0_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ADS_HB0_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ADS_HB1_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ADS_HB1_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ADS_HB1_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31F8_DP_ENCODER0_P0 0x31F8
+#define ADS_HB2_DP_ENCODER0_P0_FLDMASK 0xff
+#define ADS_HB2_DP_ENCODER0_P0_FLDMASK_POS 0
+#define ADS_HB2_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define ADS_HB3_DP_ENCODER0_P0_FLDMASK 0xff00
+#define ADS_HB3_DP_ENCODER0_P0_FLDMASK_POS 8
+#define ADS_HB3_DP_ENCODER0_P0_FLDMASK_LEN 8
+
+#define REG_31FC_DP_ENCODER0_P0 0x31FC
+#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK 0x3
+#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK_POS 0
+#define VIDEO_ARBITER_DE_LAST_NUM0_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK 0xc
+#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK_POS 2
+#define VIDEO_ARBITER_DE_LAST_NUM1_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK 0x30
+#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK_POS 4
+#define VIDEO_ARBITER_DE_LAST_NUM2_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK 0xc0
+#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK_POS 6
+#define VIDEO_ARBITER_DE_LAST_NUM3_SW_DP_ENCODER0_P0_FLDMASK_LEN 2
+
+#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK 0x100
+#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK_POS 8
+#define HDE_NUM_EVEN_EN_SW_LANE0_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK 0x200
+#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK_POS 9
+#define HDE_NUM_EVEN_EN_SW_LANE1_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK 0x400
+#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK_POS 10
+#define HDE_NUM_EVEN_EN_SW_LANE2_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK 0x800
+#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK_POS 11
+#define HDE_NUM_EVEN_EN_SW_LANE3_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK 0x1000
+#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK_POS 12
+#define DE_LAST_NUM_SW_DP_ENCODER0_P0_FLDMASK_LEN 1
+
+#define REG_3200_DP_ENCODER1_P0 0x3200
+#define SDP_DB0_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB0_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB1_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB1_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB1_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3204_DP_ENCODER1_P0 0x3204
+#define SDP_DB2_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB2_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB2_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB3_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB3_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB3_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3208_DP_ENCODER1_P0 0x3208
+#define SDP_DB4_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB4_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB4_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB5_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB5_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB5_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_320C_DP_ENCODER1_P0 0x320C
+#define SDP_DB6_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB6_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB6_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB7_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB7_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB7_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3210_DP_ENCODER1_P0 0x3210
+#define SDP_DB8_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB8_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB8_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB9_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB9_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB9_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3214_DP_ENCODER1_P0 0x3214
+#define SDP_DB10_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB10_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB10_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB11_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB11_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB11_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3218_DP_ENCODER1_P0 0x3218
+#define SDP_DB12_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB12_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB12_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB13_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB13_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB13_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_321C_DP_ENCODER1_P0 0x321C
+#define SDP_DB14_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB14_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB14_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB15_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB15_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB15_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3220_DP_ENCODER1_P0 0x3220
+#define SDP_DB16_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB16_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB16_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB17_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB17_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB17_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3224_DP_ENCODER1_P0 0x3224
+#define SDP_DB18_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB18_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB18_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB19_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB19_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB19_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3228_DP_ENCODER1_P0 0x3228
+#define SDP_DB20_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB20_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB20_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB21_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB21_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB21_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_322C_DP_ENCODER1_P0 0x322C
+#define SDP_DB22_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB22_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB22_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB23_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB23_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB23_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3230_DP_ENCODER1_P0 0x3230
+#define SDP_DB24_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB24_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB24_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB25_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB25_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB25_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3234_DP_ENCODER1_P0 0x3234
+#define SDP_DB26_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB26_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB26_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB27_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB27_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB27_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3238_DP_ENCODER1_P0 0x3238
+#define SDP_DB28_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB28_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB28_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB29_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB29_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB29_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_323C_DP_ENCODER1_P0 0x323C
+#define SDP_DB30_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB30_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB30_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB31_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB31_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB31_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3240_DP_ENCODER1_P0 0x3240
+#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB0_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB1_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3244_DP_ENCODER1_P0 0x3244
+#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB2_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB3_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3248_DP_ENCODER1_P0 0x3248
+#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB4_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB5_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_324C_DP_ENCODER1_P0 0x324C
+#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB6_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB7_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3250_DP_ENCODER1_P0 0x3250
+#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB8_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB9_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3254_DP_ENCODER1_P0 0x3254
+#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB10_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB11_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3258_DP_ENCODER1_P0 0x3258
+#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB12_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB13_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_325C_DP_ENCODER1_P0 0x325C
+#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB14_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB15_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3260_DP_ENCODER1_P0 0x3260
+#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB16_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB17_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3264_DP_ENCODER1_P0 0x3264
+#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB18_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB19_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3268_DP_ENCODER1_P0 0x3268
+#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB20_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB21_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_326C_DP_ENCODER1_P0 0x326C
+#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB22_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB23_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3270_DP_ENCODER1_P0 0x3270
+#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB24_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB25_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3274_DP_ENCODER1_P0 0x3274
+#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB26_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB27_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3278_DP_ENCODER1_P0 0x3278
+#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB28_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB29_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_327C_DP_ENCODER1_P0 0x327C
+#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK 0xff
+#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DB30_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK 0xff00
+#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DB31_R_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3280_DP_ENCODER1_P0 0x3280
+#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK 0x1f
+#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_PACKET_TYPE_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK 0x20
+#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK_POS 5
+#define SDP_PACKET_W_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK 0x40
+#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK_POS 6
+#define SDP_PACKET_R_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_328C_DP_ENCODER1_P0 0x328C
+#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK 0x1
+#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_SW_HW_SEL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK 0x2
+#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK_POS 1
+#define VSC_SRAM_HW_RST_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK 0x4
+#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK_POS 2
+#define VSC_SRAM_SW_RST_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK 0x8
+#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_POS 3
+#define VSC_SRAM_HW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK 0x10
+#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK_POS 4
+#define VSC_SRAM_HW_FULL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK 0x20
+#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK_POS 5
+#define VSC_SRAM_HW_FULL_CLR_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK 0x40
+#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK_POS 6
+#define VSC_DATA_TOGGLE_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK 0x80
+#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK_POS 7
+#define VSC_DATA_RDY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK 0x100
+#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_SRAM_SW_EMPTY_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_3290_DP_ENCODER1_P0 0x3290
+#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE0_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE1_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3294_DP_ENCODER1_P0 0x3294
+#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE2_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE3_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_3298_DP_ENCODER1_P0 0x3298
+#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE4_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE5_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_329C_DP_ENCODER1_P0 0x329C
+#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE6_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE7_VESA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32A0_DP_ENCODER1_P0 0x32A0
+#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK 0x1
+#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_SW_HW_SEL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK 0x2
+#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK_POS 1
+#define VSC_SRAM_HW_RST_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK 0x4
+#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK_POS 2
+#define VSC_SRAM_SW_RST_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK 0x8
+#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_POS 3
+#define VSC_SRAM_HW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK 0x10
+#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK_POS 4
+#define VSC_SRAM_HW_FULL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK 0x20
+#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK_POS 5
+#define VSC_SRAM_HW_FULL_CLR_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK 0x40
+#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK_POS 6
+#define VSC_DATA_TOGGLE_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK 0x80
+#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK_POS 7
+#define VSC_DATA_RDY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK 0x100
+#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_SRAM_SW_EMPTY_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_32A4_DP_ENCODER1_P0 0x32A4
+#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE0_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE1_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32A8_DP_ENCODER1_P0 0x32A8
+#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE2_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE3_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32AC_DP_ENCODER1_P0 0x32AC
+#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE4_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE5_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32B0_DP_ENCODER1_P0 0x32B0
+#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_BYTE6_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK 0xff00
+#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VSC_DATA_BYTE7_CEA_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32B4_DP_ENCODER1_P0 0x32B4
+#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK 0x1
+#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_DATA_SW_CAN_WRITE_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK 0x2
+#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK_POS 1
+#define VSC_DATA_SW_CAN_WRITE_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK 0x4
+#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK_POS 2
+#define VSC_DATA_TRANSMIT_SEL_VESA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK 0x8
+#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK_POS 3
+#define VSC_DATA_TRANSMIT_SEL_CEA_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_32C0_DP_ENCODER1_P0 0x32C0
+#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_MASK_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32C4_DP_ENCODER1_P0 0x32C4
+#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_CLR_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32C8_DP_ENCODER1_P0 0x32C8
+#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_FORCE_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32CC_DP_ENCODER1_P0 0x32CC
+#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_STATUS_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32D0_DP_ENCODER1_P0 0x32D0
+#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_FINAL_STATUS_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32D4_DP_ENCODER1_P0 0x32D4
+#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_MASK_51_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32D8_DP_ENCODER1_P0 0x32D8
+#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_CLR_51_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32DC_DP_ENCODER1_P0 0x32DC
+#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_FORCE_51_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32E0_DP_ENCODER1_P0 0x32E0
+#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_STATUS_51_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32E4_DP_ENCODER1_P0 0x32E4
+#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK 0xffff
+#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK_POS 0
+#define IRQ_FINAL_STATUS_51_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32E8_DP_ENCODER1_P0 0x32E8
+#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK 0x7f
+#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_SRAM_WRITE_ADDR_0_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK 0x7f00
+#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK_POS 8
+#define AUDIO_SRAM_WRITE_ADDR_1_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define REG_32EC_DP_ENCODER1_P0 0x32EC
+#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK 0x7f
+#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_SRAM_WRITE_ADDR_2_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK 0x7f00
+#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK_POS 8
+#define AUDIO_SRAM_WRITE_ADDR_3_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define REG_32F0_DP_ENCODER1_P0 0x32F0
+#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define M_CODE_FEC_MERGE_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_32F4_DP_ENCODER1_P0 0x32F4
+#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK 0xff
+#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define M_CODE_FEC_MERGE_1_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_32F8_DP_ENCODER1_P0 0x32F8
+#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xff
+#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 0
+#define MSA_UPDATE_LINE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK 0x200
+#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK_POS 9
+#define SDP_SPLIT_BUG_FIX_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK 0x400
+#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK_POS 10
+#define MSA_MUTE_MASK_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK 0x3000
+#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
+#define MSA_UPDATE_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK 0xc000
+#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK_POS 14
+#define VIDEO_MUTE_TOGGLE_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define REG_3300_DP_ENCODER1_P0 0x3300
+#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK 0x1
+#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_AFIFO_CNT_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK 0x2
+#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK_POS 1
+#define AUDIO_SRAM_CNT_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK 0xf0
+#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK_POS 4
+#define AUDIO_AFIFO_CNT_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK 0x300
+#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VIDEO_AFIFO_RDY_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define REG_3304_DP_ENCODER1_P0 0x3304
+#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK 0x7f
+#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_SRAM_CNT_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK 0x100
+#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK_POS 8
+#define AU_PRTY_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK 0x200
+#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK_POS 9
+#define AU_CH_STS_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK 0x400
+#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK_POS 10
+#define AUDIO_VALIDITY_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK 0x800
+#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK_POS 11
+#define AUDIO_RESERVED_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK 0x1000
+#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK_POS 12
+#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_3320_DP_ENCODER1_P0 0x3320
+#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0x1ff
+#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_PATTERN_GEN_DSTB_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 9
+
+#define REG_3324_DP_ENCODER1_P0 0x3324
+#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK 0x300
+#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK_POS 8
+#define AUDIO_SOURCE_MUX_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define AUDIO_PATTERN_GEN_CH_NUM_DP_ENCODER1_P0_FLDMASK 0x3000
+#define AUDIO_PATGEN_CH_NUM_DP_ENCODER1_P0_FLDMASK_POS 12
+#define AUDIO_PATTERN_GEN_CH_NUM_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define AUDIO_PATTERN_GEN_FS_SEL_DP_ENCODER1_P0_FLDMASK 0xc000
+#define AUDIO_PATGEN_FS_SEL_DP_ENCODER1_P0_FLDMASK_POS 14
+#define AUDIO_PATTERN_GEN_FS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define REG_3328_DP_ENCODER1_P0 0x3328
+#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK 0x1
+#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK 0x2
+#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_POS 1
+#define HSYNC_DETECT_POL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK 0x4
+#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_POS 2
+#define HTOTAL_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK 0x8
+#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_POS 3
+#define HDE_DETECT_STABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_332C_DP_ENCODER1_P0 0x332C
+#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
+#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3330_DP_ENCODER1_P0 0x3330
+#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
+#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VDE_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3334_DP_ENCODER1_P0 0x3334
+#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
+#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define HTOTAL_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3338_DP_ENCODER1_P0 0x3338
+#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK 0xffff
+#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define HDE_DETECT_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3340_DP_ENCODER1_P0 0x3340
+#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK 0x1
+#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define BIST_FAIL_VIDEO_L0_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK 0x2
+#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK_POS 1
+#define BIST_FAIL_VIDEO_L1_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK 0x4
+#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK_POS 2
+#define BIST_FAIL_VIDEO_L2_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK 0x8
+#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK_POS 3
+#define BIST_FAIL_VIDEO_L3_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK 0x10
+#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK_POS 4
+#define BIST_FAIL_AUDIO_L0_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK 0x20
+#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK_POS 5
+#define BIST_FAIL_AUDIO_L1_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK 0x40
+#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK_POS 6
+#define BIST_FAIL_AUDIO_L2_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK 0x80
+#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK_POS 7
+#define BIST_FAIL_AUDIO_L3_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK 0x100
+#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK_POS 8
+#define BIST_FAIL_VSC_VESA_HW_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK 0x200
+#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK_POS 9
+#define BIST_FAIL_VSC_CEA_HW_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK 0x400
+#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK_POS 10
+#define BIST_FAIL_VSC_VESA_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK 0x800
+#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK_POS 11
+#define BIST_FAIL_VSC_CEA_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK 0x7000
+#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
+#define LR_FIELD_SYNC_SEL_DP_ENCODER1_P0_FLDMASK_LEN 3
+
+#define REG_3344_DP_ENCODER1_P0 0x3344
+#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
+#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_CH1_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
+#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DP_CH2_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define REG_3348_DP_ENCODER1_P0 0x3348
+#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
+#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_CH3_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
+#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DP_CH4_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define REG_334C_DP_ENCODER1_P0 0x334C
+#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
+#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_CH5_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
+#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DP_CH6_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define REG_3350_DP_ENCODER1_P0 0x3350
+#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f
+#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_CH7_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK 0x1f00
+#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DP_CH8_MATRIX_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define REG_3354_DP_ENCODER1_P0 0x3354
+#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK 0x7f
+#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_S2P_LAUNCH_CFG_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK 0x1000
+#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK_POS 12
+#define AUDIO_HAYDN_EN_FORCE_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK 0xf00
+#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK_POS 8
+#define AUDIO_HAYDN_FORMAT_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define REG_3358_DP_ENCODER1_P0 0x3358
+#define TU_SIZE_DP_ENCODER1_P0_FLDMASK 0x7f
+#define TU_SIZE_DP_ENCODER1_P0_FLDMASK_POS 0
+#define TU_SIZE_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK 0x80
+#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK_POS 7
+#define TU_CALC_SW_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_335C_DP_ENCODER1_P0 0x335C
+#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SYMBOL_DATA_PER_TU_SW_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3360_DP_ENCODER1_P0 0x3360
+#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK 0x7fff
+#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SYMBOL_DATA_PER_TU_SW_1_DP_ENCODER1_P0_FLDMASK_LEN 15
+
+#define REG_3364_DP_ENCODER1_P0 0x3364
+#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK 0xfff
+#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK_POS 0
+#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENCODER1_P0_FLDMASK_LEN 12
+
+#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK 0xf000
+#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK_POS 12
+#define FIFO_READ_START_POINT_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define REG_3368_DP_ENCODER1_P0 0x3368
+#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK 0x3
+#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK 0x4
+#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK_POS 2
+#define VIDEO_STABLE_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xf0
+#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 4
+#define VIDEO_STABLE_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK 0x100
+#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_DP13_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK 0x600
+#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK_POS 9
+#define VIDEO_PIXEL_SWAP_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK 0x3000
+#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK_POS 12
+#define BS2BS_MODE_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define REG_336C_DP_ENCODER1_P0 0x336C
+#define DSC_EN_DP_ENCODER1_P0_FLDMASK 0x1
+#define DSC_EN_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DSC_EN_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK 0x2
+#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK_POS 1
+#define DSC_BYTE_SWAP_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK 0xf0
+#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK_POS 4
+#define DSC_SLICE_NUM_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK 0xf00
+#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DSC_CHUNK_REMAINDER_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define REG_3370_DP_ENCODER1_P0 0x3370
+#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK 0xffff
+#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DSC_CHUNK_NUM_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33AC_DP_ENCODER1_P0 0x33AC
+#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK 0xffff
+#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK_POS 0
+#define TEST_CRC_R_CR_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33B0_DP_ENCODER1_P0 0x33B0
+#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK 0xffff
+#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK_POS 0
+#define TEST_CRC_G_Y_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33B4_DP_ENCODER1_P0 0x33B4
+#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK 0xffff
+#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK_POS 0
+#define TEST_CRC_B_CB_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33B8_DP_ENCODER1_P0 0x33B8
+#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK 0xf
+#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK_POS 0
+#define TEST_CRC_WRAP_CNT_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK 0x1f0
+#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK_POS 4
+#define CRC_COLOR_FORMAT_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK 0x200
+#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK_POS 9
+#define CRC_TEST_SINK_START_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_33BC_DP_ENCODER1_P0 0x33BC
+#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK 0x1fff
+#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK_POS 0
+#define CRC_TEST_CONFIG_DP_ENCODER1_P0_FLDMASK_LEN 13
+
+#define REG_33C0_DP_ENCODER1_P0 0x33C0
+#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK 0x7f
+#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VIDEO_TU_VALUE_DP_ENCODER1_P0_FLDMASK_LEN 7
+
+#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0xf00
+#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 8
+#define DP_TX_MIXER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0xf000
+#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 12
+#define DP_TX_SDP_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define REG_33C4_DP_ENCODER1_P0 0x33C4
+#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0x1f
+#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_TX_VIDEO_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 5
+
+#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK 0x60
+#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_POS 5
+#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENCODER1_P0_FLDMASK_LEN 2
+
+#define REG_33C8_DP_ENCODER1_P0 0x33C8
+#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VIDEO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33CC_DP_ENCODER1_P0 0x33CC
+#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK 0xff
+#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VIDEO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_33D0_DP_ENCODER1_P0 0x33D0
+#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_M_CODE_READ_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33D4_DP_ENCODER1_P0 0x33D4
+#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK 0xff
+#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define AUDIO_M_CODE_READ_1_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define REG_33D8_DP_ENCODER1_P0 0x33D8
+#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK 0xff
+#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VSC_EXT_CFG_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK 0x100
+#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 8
+#define SDP_SPLIT_FIFO_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK 0x200
+#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK_POS 9
+#define SDP_SPLIT_FIFO_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x400
+#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 10
+#define SDP_SPLIT_FIFO_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK 0xf000
+#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK_POS 12
+#define SDP_SPLIT_INSERT_INVALID_CNT_THRD_DP_ENCODER1_P0_FLDMASK_LEN 4
+
+#define REG_33DC_DP_ENCODER1_P0 0x33DC
+#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK 0x1
+#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK_POS 0
+#define VIDEO_SRAM0_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x2
+#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 1
+#define VIDEO_SRAM0_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK 0x4
+#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK_POS 2
+#define VIDEO_SRAM1_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x8
+#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 3
+#define VIDEO_SRAM1_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK 0x10
+#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK_POS 4
+#define VIDEO_SRAM2_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x20
+#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 5
+#define VIDEO_SRAM2_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK 0x40
+#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK_POS 6
+#define VIDEO_SRAM3_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x80
+#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 7
+#define VIDEO_SRAM3_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK 0x100
+#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 8
+#define VIDEO_SRAM0_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x200
+#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 9
+#define VIDEO_SRAM0_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK 0x400
+#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 10
+#define VIDEO_SRAM1_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x800
+#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 11
+#define VIDEO_SRAM1_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK 0x1000
+#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 12
+#define VIDEO_SRAM2_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x2000
+#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 13
+#define VIDEO_SRAM2_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK 0x4000
+#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 14
+#define VIDEO_SRAM3_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK 0x8000
+#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_POS 15
+#define VIDEO_SRAM3_EMPTY_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_33E0_DP_ENCODER1_P0 0x33E0
+#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK 0xffff
+#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK_POS 0
+#define BS2BS_CNT_SW_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33E4_DP_ENCODER1_P0 0x33E4
+#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define MIXER_STATE_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33E8_DP_ENCODER1_P0 0x33E8
+#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK 0xffff
+#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define MIXER_STATE_1_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33EC_DP_ENCODER1_P0 0x33EC
+#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK 0xff
+#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK_POS 0
+#define MIXER_STATE_2_DP_ENCODER1_P0_FLDMASK_LEN 8
+
+#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK 0x200
+#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK_POS 9
+#define VIDEO_PERIOD_ENABLE_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK 0x400
+#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK_POS 10
+#define BS2BS_CNT_SW_SEL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK 0x800
+#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK_POS 11
+#define AUDIO_SRAM_FULL_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK 0x1000
+#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK_POS 12
+#define AUDIO_SRAM_FULL_CLR_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK 0x2000
+#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK_POS 13
+#define AUDIO_SRAM_EMPTY_DP_ENCODER1_P0_FLDMASK_LEN 1
+
+#define REG_33F0_DP_ENCODER1_P0 0x33F0
+#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_ENCODER_DUMMY_RW_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33F4_DP_ENCODER1_P0 0x33F4
+#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK 0xffff
+#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_ENCODER_DUMMY_RW_1_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33F8_DP_ENCODER1_P0 0x33F8
+#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK 0xffff
+#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_ENCODER_DUMMY_R_0_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_33FC_DP_ENCODER1_P0 0x33FC
+#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK 0xffff
+#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK_POS 0
+#define DP_ENCODER_DUMMY_R_1_DP_ENCODER1_P0_FLDMASK_LEN 16
+
+#define REG_3400_DP_TRANS_P0 0x3400
+#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK 0x3
+#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_POS 0
+#define PRE_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK 0xc
+#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_POS 2
+#define PRE_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK 0x30
+#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_POS 4
+#define PRE_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK 0xc0
+#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_POS 6
+#define PRE_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK 0x700
+#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK_POS 8
+#define PRE_MISC_PORT_MUX_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define HDCP_SEL_DP_TRANS_P0_FLDMASK 0x800
+#define HDCP_SEL_DP_TRANS_P0_FLDMASK_POS 11
+#define HDCP_SEL_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define PATTERN1_EN_DP_TRANS_P0_FLDMASK 0x1000
+#define PATTERN1_EN_DP_TRANS_P0_FLDMASK_POS 12
+#define PATTERN1_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define PATTERN2_EN_DP_TRANS_P0_FLDMASK 0x2000
+#define PATTERN2_EN_DP_TRANS_P0_FLDMASK_POS 13
+#define PATTERN2_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define PATTERN3_EN_DP_TRANS_P0_FLDMASK 0x4000
+#define PATTERN3_EN_DP_TRANS_P0_FLDMASK_POS 14
+#define PATTERN3_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define PATTERN4_EN_DP_TRANS_P0_FLDMASK 0x8000
+#define PATTERN4_EN_DP_TRANS_P0_FLDMASK_POS 15
+#define PATTERN4_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3404_DP_TRANS_P0 0x3404
+#define DP_SCR_EN_DP_TRANS_P0_FLDMASK 0x1
+#define DP_SCR_EN_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_SCR_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK 0x2
+#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK_POS 1
+#define ALTER_SCRAMBLER_RESET_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK 0x4
+#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK_POS 2
+#define SCRAMB_BYPASS_IN_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK 0x8
+#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK_POS 3
+#define SCRAMB_BYPASS_MASK_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK 0x30
+#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK_POS 4
+#define INDEX_SCR_MODE_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK 0x40
+#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK_POS 6
+#define PAT_INIT_DISPARITY_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK 0x80
+#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK_POS 7
+#define TPS_DISPARITY_RESET_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3408_DP_TRANS_P0 0x3408
+#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK 0x3
+#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK_POS 0
+#define LANE_SKEW_SEL_LANE0_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK 0xc
+#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK_POS 2
+#define LANE_SKEW_SEL_LANE1_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK 0x30
+#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK_POS 4
+#define LANE_SKEW_SEL_LANE2_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK 0xc0
+#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK_POS 6
+#define LANE_SKEW_SEL_LANE3_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK 0x300
+#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_POS 8
+#define POST_MISC_LANE0_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK 0xc00
+#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_POS 10
+#define POST_MISC_LANE1_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK 0x3000
+#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_POS 12
+#define POST_MISC_LANE2_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK 0xc000
+#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_POS 14
+#define POST_MISC_LANE3_MUX_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define REG_340C_DP_TRANS_P0 0x340C
+#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK 0x100
+#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK_POS 8
+#define TOP_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK 0x200
+#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK_POS 9
+#define LANE0_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK 0x400
+#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK_POS 10
+#define LANE1_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK 0x800
+#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK_POS 11
+#define LANE2_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK 0x1000
+#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK_POS 12
+#define LANE3_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK 0x2000
+#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK_POS 13
+#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK 0x4000
+#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK_POS 14
+#define HDCP13_RST_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK 0x8000
+#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK_POS 15
+#define HDCP22_RST_SW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3410_DP_TRANS_P0 0x3410
+#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK 0xf
+#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK_POS 0
+#define HPD_DEB_THD_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define HPD_INT_THD_DP_TRANS_P0_FLDMASK 0xf0
+#define HPD_INT_THD_DP_TRANS_P0_FLDMASK_POS 4
+#define HPD_INT_THD_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK 0xf00
+#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK_POS 8
+#define HPD_DISC_THD_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK 0xf000
+#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK_POS 12
+#define HPD_CONN_THD_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define REG_3414_DP_TRANS_P0 0x3414
+#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK 0x1
+#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK_POS 0
+#define HPD_OVR_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HPD_SET_DP_TRANS_P0_FLDMASK 0x2
+#define HPD_SET_DP_TRANS_P0_FLDMASK_POS 1
+#define HPD_SET_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HPD_DB_DP_TRANS_P0_FLDMASK 0x4
+#define HPD_DB_DP_TRANS_P0_FLDMASK_POS 2
+#define HPD_DB_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3418_DP_TRANS_P0 0x3418
+#define IRQ_CLR_DP_TRANS_P0_FLDMASK 0xf
+#define IRQ_CLR_DP_TRANS_P0_FLDMASK_POS 0
+#define IRQ_CLR_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_MASK_DP_TRANS_P0_FLDMASK 0xf0
+#define IRQ_MASK_DP_TRANS_P0_FLDMASK_POS 4
+#define IRQ_MASK_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_FORCE_DP_TRANS_P0_FLDMASK 0xf00
+#define IRQ_FORCE_DP_TRANS_P0_FLDMASK_POS 8
+#define IRQ_FORCE_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_STATUS_DP_TRANS_P0_FLDMASK 0xf000
+#define IRQ_STATUS_DP_TRANS_P0_FLDMASK_POS 12
+#define IRQ_STATUS_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define REG_341C_DP_TRANS_P0 0x341C
+#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK 0xf
+#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK_POS 0
+#define IRQ_CLR_51_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK 0xf0
+#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK_POS 4
+#define IRQ_MASK_51_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK 0xf00
+#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK_POS 8
+#define IRQ_FORCE_51_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK 0xf000
+#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK_POS 12
+#define IRQ_STATUS_51_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define REG_3420_DP_TRANS_P0 0x3420
+#define HPD_STATUS_DP_TRANS_P0_FLDMASK 0x1
+#define HPD_STATUS_DP_TRANS_P0_FLDMASK_POS 0
+#define HPD_STATUS_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3428_DP_TRANS_P0 0x3428
+#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK 0x1
+#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_BIT_REVERSE_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK 0x2
+#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 1
+#define POST_MISC_BIT_REVERSE_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK 0x4
+#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 2
+#define POST_MISC_BIT_REVERSE_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK 0x8
+#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 3
+#define POST_MISC_BIT_REVERSE_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK 0x10
+#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 4
+#define POST_MISC_PN_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK 0x20
+#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 5
+#define POST_MISC_PN_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK 0x40
+#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 6
+#define POST_MISC_PN_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK 0x80
+#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 7
+#define POST_MISC_PN_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK 0x100
+#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_POS 8
+#define POST_MISC_DATA_SWAP_EN_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK 0x200
+#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_POS 9
+#define POST_MISC_DATA_SWAP_EN_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK 0x400
+#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_POS 10
+#define POST_MISC_DATA_SWAP_EN_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK 0x800
+#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_POS 11
+#define POST_MISC_DATA_SWAP_EN_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_342C_DP_TRANS_P0 0x342C
+#define XTAL_FREQ_DP_TRANS_P0_FLDMASK 0xff
+#define XTAL_FREQ_DP_TRANS_P0_FLDMASK_POS 0
+#define XTAL_FREQ_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3430_DP_TRANS_P0 0x3430
+#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK 0x3
+#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK_POS 0
+#define HPD_INT_THD_ECO_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define REG_3440_DP_TRANS_P0 0x3440
+#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK 0xf
+#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_EN_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK 0x70
+#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK_POS 4
+#define PGM_PAT_SEL_L0_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK 0x700
+#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK_POS 8
+#define PGM_PAT_SEL_L1_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK 0x7000
+#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK_POS 12
+#define PGM_PAT_SEL_L2_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define REG_3444_DP_TRANS_P0 0x3444
+#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK 0x7
+#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_SEL_L3_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define PRBS_EN_DP_TRANS_P0_FLDMASK 0x8
+#define PRBS_EN_DP_TRANS_P0_FLDMASK_POS 3
+#define PRBS_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3448_DP_TRANS_P0 0x3448
+#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L0_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_344C_DP_TRANS_P0 0x344C
+#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L0_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3450_DP_TRANS_P0 0x3450
+#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK 0xff
+#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L0_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3454_DP_TRANS_P0 0x3454
+#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L1_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3458_DP_TRANS_P0 0x3458
+#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L1_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_345C_DP_TRANS_P0 0x345C
+#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK 0xff
+#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L1_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3460_DP_TRANS_P0 0x3460
+#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L2_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3464_DP_TRANS_P0 0x3464
+#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L2_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3468_DP_TRANS_P0 0x3468
+#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK 0xff
+#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L2_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_346C_DP_TRANS_P0 0x346C
+#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L3_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3470_DP_TRANS_P0 0x3470
+#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK 0xffff
+#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L3_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3474_DP_TRANS_P0 0x3474
+#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK 0xff
+#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK_POS 0
+#define PGM_PAT_L3_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3478_DP_TRANS_P0 0x3478
+#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK 0x1
+#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK_POS 0
+#define CP2520_PATTERN1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK 0x2
+#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK_POS 1
+#define CP2520_PATTERN2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x10
+#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 4
+#define CP2520_PATTERN1_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x20
+#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 5
+#define CP2520_PATTERN1_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x40
+#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 6
+#define CP2520_PATTERN1_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x80
+#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 7
+#define CP2520_PATTERN1_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x100
+#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 8
+#define CP2520_PATTERN1_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x200
+#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 9
+#define CP2520_PATTERN1_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x400
+#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 10
+#define CP2520_PATTERN1_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x800
+#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 11
+#define CP2520_PATTERN1_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_347C_DP_TRANS_P0 0x347C
+#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x1
+#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 0
+#define CP2520_PATTERN2_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x2
+#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 1
+#define CP2520_PATTERN2_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x4
+#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 2
+#define CP2520_PATTERN2_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8
+#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 3
+#define CP2520_PATTERN2_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x10
+#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 4
+#define CP2520_PATTERN2_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x20
+#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 5
+#define CP2520_PATTERN2_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x40
+#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 6
+#define CP2520_PATTERN2_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x80
+#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 7
+#define CP2520_PATTERN2_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x100
+#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 8
+#define CP2520_PATTERN3_KCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x200
+#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 9
+#define CP2520_PATTERN3_KCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x400
+#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 10
+#define CP2520_PATTERN3_KCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x800
+#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 11
+#define CP2520_PATTERN3_KCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x1000
+#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 12
+#define CP2520_PATTERN3_DCODE_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x2000
+#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 13
+#define CP2520_PATTERN3_DCODE_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x4000
+#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 14
+#define CP2520_PATTERN3_DCODE_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8000
+#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 15
+#define CP2520_PATTERN3_DCODE_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3480_DP_TRANS_P0 0x3480
+#define DP_EN_DP_TRANS_P0_FLDMASK 0x1
+#define DP_EN_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK 0x2
+#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK_POS 1
+#define HDCP_CAPABLE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK 0x4
+#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK_POS 2
+#define SELECT_INTERNAL_AN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define AN_FREERUN_DP_TRANS_P0_FLDMASK 0x8
+#define AN_FREERUN_DP_TRANS_P0_FLDMASK_POS 3
+#define AN_FREERUN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define KM_GENERATED_DP_TRANS_P0_FLDMASK 0x10
+#define KM_GENERATED_DP_TRANS_P0_FLDMASK_POS 4
+#define KM_GENERATED_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK 0x1000
+#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK_POS 12
+#define REQ_BLOCK_CIPHER_AUTH_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK 0x2000
+#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK_POS 13
+#define HDCP_1LANE_SEL_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK 0x4000
+#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK_POS 14
+#define HDCP_24LANE_SEL_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define MST_EN_DP_TRANS_P0_FLDMASK 0x8000
+#define MST_EN_DP_TRANS_P0_FLDMASK_POS 15
+#define MST_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_34A4_DP_TRANS_P0 0x34A4
+#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK 0x1
+#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK_POS 0
+#define EN_COPY_2LANE_MSA_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK 0x2
+#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK_POS 1
+#define EN_COPY_4LANE_MSA_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define LANE_NUM_DP_TRANS_P0_FLDMASK 0xc
+#define LANE_NUM_DP_TRANS_P0_FLDMASK_POS 2
+#define LANE_NUM_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK 0x10
+#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK_POS 4
+#define HDCP22_AUTH_DONE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK 0x20
+#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK_POS 5
+#define DISCARD_UNUSED_CIPHER_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK 0x40
+#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK_POS 6
+#define HDCP22_CIPHER_REVERSE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK 0x80
+#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK_POS 7
+#define MST_DELAY_CYCLE_FLAG_SEL_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK 0xf00
+#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK_POS 8
+#define TEST_CONFIG_HDCP22_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK 0x1000
+#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK_POS 12
+#define R0_AVAILABLE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK 0x2000
+#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK_POS 13
+#define DPES_TX_HDCP22_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK 0x4000
+#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK_POS 14
+#define DP_AES_OUT_RDY_L_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REPEATER_I_DP_TRANS_P0_FLDMASK 0x8000
+#define REPEATER_I_DP_TRANS_P0_FLDMASK_POS 15
+#define REPEATER_I_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_34A8_DP_TRANS_P0 0x34A8
+#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK 0xff00
+#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK_POS 8
+#define TEST_CONFIG_HDCP13_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_34D0_DP_TRANS_P0 0x34D0
+#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK 0xff
+#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK_POS 0
+#define TX_HDCP22_TYPE_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK 0xf00
+#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK_POS 8
+#define PIPE_DELAY_EN_CNT_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define PIPE_DELAY_DP_TRANS_P0_FLDMASK 0xf000
+#define PIPE_DELAY_DP_TRANS_P0_FLDMASK_POS 12
+#define PIPE_DELAY_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define REG_34D4_DP_TRANS_P0 0x34D4
+#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_L_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34D8_DP_TRANS_P0 0x34D8
+#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_L_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34DC_DP_TRANS_P0 0x34DC
+#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_L_2_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34E0_DP_TRANS_P0 0x34E0
+#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_L_3_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34E4_DP_TRANS_P0 0x34E4
+#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK 0xffff
+#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP_TYPE_TX_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34E8_DP_TRANS_P0 0x34E8
+#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK 0xffff
+#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP_TYPE_TX_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34EC_DP_TRANS_P0 0x34EC
+#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK 0xffff
+#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP_TYPE_TX_2_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34F0_DP_TRANS_P0 0x34F0
+#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK 0xffff
+#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP_TYPE_TX_3_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_34F4_DP_TRANS_P0 0x34F4
+#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK 0xff
+#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK_POS 0
+#define SST_HDCP_TYPE_TX_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK 0xf00
+#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK_POS 8
+#define PIPE_OV_VALUE_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK 0x1000
+#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK_POS 12
+#define PIPE_OV_ENABLE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_34F8_DP_TRANS_P0 0x34F8
+#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK 0x4000
+#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK_POS 14
+#define DP_AES_OUT_RDY_H_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_34FC_DP_TRANS_P0 0x34FC
+#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK 0xff
+#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP_4P_TO_2P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK 0xff00
+#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_POS 8
+#define HDCP_2P_TO_4P_FIFO_RST_CHK_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3500_DP_TRANS_P0 0x3500
+#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_H_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3504_DP_TRANS_P0 0x3504
+#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_H_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3508_DP_TRANS_P0 0x3508
+#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_H_2_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_350C_DP_TRANS_P0 0x350C
+#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_AES_INCTR_H_3_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3510_DP_TRANS_P0 0x3510
+#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK 0xff
+#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK_POS 0
+#define HDCP22_TYPE_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3540_DP_TRANS_P0 0x3540
+#define FEC_EN_DP_TRANS_P0_FLDMASK 0x1
+#define FEC_EN_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_EN_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_END_MODE_DP_TRANS_P0_FLDMASK 0x6
+#define FEC_END_MODE_DP_TRANS_P0_FLDMASK_POS 1
+#define FEC_END_MODE_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK 0x8
+#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK_POS 3
+#define FEC_CLOCK_EN_MODE_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK 0xf0
+#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK_POS 4
+#define FEC_FIFO_READ_START_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK 0xf00
+#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK_POS 8
+#define FEC_FIFO_UNDER_POINT_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK 0xf000
+#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK_POS 12
+#define FEC_FIFO_OVER_POINT_DP_TRANS_P0_FLDMASK_LEN 4
+
+#define REG_3544_DP_TRANS_P0 0x3544
+#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK 0x1
+#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_FIFO_RST_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK 0x2
+#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK_POS 1
+#define FEC_SUPPORT_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK 0x4
+#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK_POS 2
+#define FEC_PATTERN_NEW_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK 0x10
+#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK_POS 4
+#define FEC_INSERT_FIFO_EMPTY_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK 0x20
+#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK_POS 5
+#define FEC_INSERT_FIFO_EMPTY_CLR_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK 0x40
+#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK_POS 6
+#define FEC_INSERT_FIFO_FULL_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK 0x80
+#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK_POS 7
+#define FEC_INSERT_FIFO_FULL_CLR_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK 0x700
+#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK_POS 8
+#define PARITY_INTERLEAVER_DATA_INVERT_PIPE_SEL_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK 0x800
+#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK_POS 11
+#define PAT_INIT_DISPARITY_FEC_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK 0x1000
+#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK_POS 12
+#define FEC_PARITY_DATA_LANE_SWAP_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3548_DP_TRANS_P0 0x3548
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK 0x7
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE0_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK 0x8
+#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK_POS 3
+#define FEC_INSERT_SYMBOL_ERROR_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK 0x70
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK_POS 4
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE1_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK 0x80
+#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK_POS 7
+#define FEC_INSERT_SYMBOL_ERROR_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK 0x700
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK_POS 8
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE2_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK 0x800
+#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK_POS 11
+#define FEC_INSERT_SYMBOL_ERROR_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK 0x7000
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK_POS 12
+#define FEC_INSERT_SYMBOL_ERROR_CNT_LANE3_DP_TRANS_P0_FLDMASK_LEN 3
+
+#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK 0x8000
+#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK_POS 15
+#define FEC_INSERT_SYMBOL_ERROR_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_354C_DP_TRANS_P0 0x354C
+#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK 0x1
+#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_CP_HIT_LANE0_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK 0x2
+#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK_POS 1
+#define FEC_CP_HIT_LANE1_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK 0x4
+#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK_POS 2
+#define FEC_CP_HIT_LANE2_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK 0x8
+#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK_POS 3
+#define FEC_CP_HIT_LANE3_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK 0x10
+#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK_POS 4
+#define FEC_CP_HIT_CLR_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0x300
+#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 8
+#define FEC_ENCODE_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0xc00
+#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 10
+#define FEC_INSERT_TOP_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define REG_3550_DP_TRANS_P0 0x3550
+#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK 0x1f
+#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_INSERT_FIFO_WCNT_DP_TRANS_P0_FLDMASK_LEN 5
+
+#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK 0x1f00
+#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK_POS 8
+#define FEC_INSERT_FIFO_RCNT_DP_TRANS_P0_FLDMASK_LEN 5
+
+#define REG_3554_DP_TRANS_P0 0x3554
+#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK 0x7f
+#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_CLK_GATE_DATA_CNT_0_DP_TRANS_P0_FLDMASK_LEN 7
+
+#define REG_3558_DP_TRANS_P0 0x3558
+#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK 0xffff
+#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_CLK_GATE_DATA_CNT_1_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_355C_DP_TRANS_P0 0x355C
+#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK 0x3
+#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK_POS 0
+#define FEC_CLK_GATE_DATA_CNT_1_1_DP_TRANS_P0_FLDMASK_LEN 2
+
+#define REG_3580_DP_TRANS_P0 0x3580
+#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK 0x1f
+#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_TX_TRANS_TESTBUS_SEL_DP_TRANS_P0_FLDMASK_LEN 5
+
+#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK 0x100
+#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK_POS 8
+#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK 0x200
+#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK_POS 9
+#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK 0x400
+#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK_POS 10
+#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK 0x800
+#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK_POS 11
+#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_FLDMASK_LEN 1
+
+#define REG_3584_DP_TRANS_P0 0x3584
+#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE0_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3588_DP_TRANS_P0 0x3588
+#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE0_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_358C_DP_TRANS_P0 0x358C
+#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK 0xff
+#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE0_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_3590_DP_TRANS_P0 0x3590
+#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE1_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3594_DP_TRANS_P0 0x3594
+#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE1_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3598_DP_TRANS_P0 0x3598
+#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK 0xff
+#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE1_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_359C_DP_TRANS_P0 0x359C
+#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE2_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35A0_DP_TRANS_P0 0x35A0
+#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE2_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35A4_DP_TRANS_P0 0x35A4
+#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK 0xff
+#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE2_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_35A8_DP_TRANS_P0 0x35A8
+#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE3_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35AC_DP_TRANS_P0 0x35AC
+#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK 0xffff
+#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE3_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35B0_DP_TRANS_P0 0x35B0
+#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK 0xff
+#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK_POS 0
+#define POST_MISC_DATA_LANE3_2_DP_TRANS_P0_FLDMASK_LEN 8
+
+#define REG_35C0_DP_TRANS_P0 0x35C0
+#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_SRC_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35C4_DP_TRANS_P0 0x35C4
+#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_MASK_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35C8_DP_TRANS_P0 0x35C8
+#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_CLR_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35CC_DP_TRANS_P0 0x35CC
+#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35D0_DP_TRANS_P0 0x35D0
+#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35D4_DP_TRANS_P0 0x35D4
+#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_RAW_STATUS_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35D8_DP_TRANS_P0 0x35D8
+#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK 0xffff
+#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK_POS 0
+#define SW_IRQ_FORCE_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35F0_DP_TRANS_P0 0x35F0
+#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_TRANSMITTER_DUMMY_RW_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35F4_DP_TRANS_P0 0x35F4
+#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_TRANSMITTER_DUMMY_RW_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35F8_DP_TRANS_P0 0x35F8
+#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_TRANSMITTER_DUMMY_R_0_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_35FC_DP_TRANS_P0 0x35FC
+#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK 0xffff
+#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK_POS 0
+#define DP_TRANSMITTER_DUMMY_R_1_DP_TRANS_P0_FLDMASK_LEN 16
+
+#define REG_3600_AUX_TX_P0 0x3600
+#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK 0x1
+#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_SW_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK 0x2
+#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_TOP_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK 0x1c
+#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK_POS 2
+#define SOFTWARE_RESET_RESERVED_AUX_TX_P0_FLDMASK_LEN 3
+
+#define AUX_CLK_EN_AUX_TX_P0_FLDMASK 0x100
+#define AUX_CLK_EN_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_CLK_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_CLK_INV_AUX_TX_P0_FLDMASK 0x200
+#define AUX_CLK_INV_AUX_TX_P0_FLDMASK_POS 9
+#define AUX_CLK_INV_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK 0xc00
+#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK_POS 10
+#define AUX_CLK_SEL_AUX_TX_P0_FLDMASK_LEN 2
+
+#define REG_3604_AUX_TX_P0 0x3604
+#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x8000
+#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 15
+#define AUX_TX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x4000
+#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 14
+#define AUX_TX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x2000
+#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 13
+#define AUX_RX_FSM_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK 0x1000
+#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_POS 12
+#define AUX_RX_PHY_SOFTWARE_RESET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK 0xff
+#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_TESTBUS_SEL_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3608_AUX_TX_P0 0x3608
+#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK 0xffff
+#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_INT_STATUS_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_360C_AUX_TX_P0 0x360C
+#define AUX_SWAP_AUX_TX_P0_FLDMASK 0x8000
+#define AUX_SWAP_AUX_TX_P0_FLDMASK_POS 15
+#define AUX_SWAP_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK 0x4000
+#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 14
+#define AUX_AUX_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK 0x2000
+#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK_POS 13
+#define AUX_TIMEOUT_CMP_MASK_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK 0x1fff
+#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TIMEOUT_THR_AUX_TX_P0_FLDMASK_LEN 13
+
+#define REG_3610_AUX_TX_P0 0x3610
+#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK 0x8000
+#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 15
+#define AUX_EDID_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK 0x7f00
+#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_EDID_ADDR_AUX_TX_P0_FLDMASK_LEN 7
+
+#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK 0x80
+#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK_POS 7
+#define AUX_MCCS_REPLY_MCU_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK 0x7f
+#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_MCCS_ADDR_AUX_TX_P0_FLDMASK_LEN 7
+
+#define REG_3614_AUX_TX_P0 0x3614
+#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK 0x4000
+#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK_POS 14
+#define AUX_TIMEOUT_THR_EXTEN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK 0x3000
+#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK_POS 12
+#define AUX_RX_AVERAGE_SEL_AUX_TX_P0_FLDMASK_LEN 2
+
+#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK 0xf00
+#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_SYNC_PATTERN_THR_AUX_TX_P0_FLDMASK_LEN 4
+
+#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK 0x80
+#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK_POS 7
+#define AUX_RX_DECODE_SEL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK 0x7f
+#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_UI_CNT_THR_AUX_TX_P0_FLDMASK_LEN 7
+
+#define REG_3618_AUX_TX_P0 0x3618
+#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK 0x400
+#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK_POS 10
+#define AUX_RX_DP_REV_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x200
+#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK_POS 9
+#define AUX_RX_FIFO_FULL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK 0x100
+#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK 0xf0
+#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_POS 4
+#define AUX_RX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_LEN 4
+
+#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK 0xf
+#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_361C_AUX_TX_P0 0x361C
+#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_DATA_BYTE_CNT_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RESERVED_RO_0_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3620_AUX_TX_P0 0x3620
+#define AUX_RD_MODE_AUX_TX_P0_FLDMASK 0x200
+#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_POS 9
+#define AUX_RD_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FIFO_READ_PULSE_TX_P0_FLDMASK 0x100
+#define AUX_RX_FIFO_R_PULSE_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_READ_PULSE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3624_AUX_TX_P0 0x3624
+#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK 0xf
+#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_FLDMASK_LEN 4
+
+#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK 0xf00
+#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_REPLY_ADDRESS_NONE_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_3628_AUX_TX_P0 0x3628
+#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK 0xfc00
+#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK_POS 10
+#define AUX_RESERVED_RO_1_AUX_TX_P0_FLDMASK_LEN 6
+
+#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK 0x3ff
+#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_PHY_STATE_AUX_TX_P0_FLDMASK_LEN 10
+
+#define REG_362C_AUX_TX_P0 0x362C
+#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK 0x1
+#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_NO_LENGTH_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK 0x2
+#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK 0xfffc
+#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK_POS 2
+#define AUX_RESERVED_RW_0_AUX_TX_P0_FLDMASK_LEN 14
+
+#define REG_3630_AUX_TX_P0 0x3630
+#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK 0x8
+#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_POS 3
+#define AUX_TX_REQUEST_READY_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_PRE_NUM_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3634_AUX_TX_P0 0x3634
+#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3638_AUX_TX_P0 0x3638
+#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK 0xf0
+#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_POS 4
+#define AUX_TX_FIFO_READ_POINTER_AUX_TX_P0_FLDMASK_LEN 4
+
+#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK 0xf
+#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_POINTER_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_363C_AUX_TX_P0 0x363C
+#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK 0x1000
+#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK_POS 12
+#define AUX_TX_FIFO_FULL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK 0x800
+#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_POS 11
+#define AUX_TX_FIFO_EMPTY_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK 0x7ff
+#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_PHY_STATE_AUX_TX_P0_FLDMASK_LEN 11
+
+#define REG_3640_AUX_TX_P0 0x3640
+#define AUX_RX_RECV_COMPLETE_IRQ_TX_P0_FLDMASK 0x40
+#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 6
+#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x20
+#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 5
+#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x10
+#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 4
+#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK 0x8
+#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 3
+#define AUX_RX_CMD_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK 0x4
+#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 2
+#define AUX_RX_ADDR_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK 0x2
+#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_RX_DATA_RECV_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK 0x1
+#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_400US_TIMEOUT_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3644_AUX_TX_P0 0x3644
+#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK 0xf
+#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK_POS 0
+#define MCU_REQUEST_COMMAND_AUX_TX_P0_FLDMASK_LEN 4
+
+#define AUX_STATE_AUX_TX_P0_FLDMASK 0xf00
+#define AUX_STATE_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_STATE_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_3648_AUX_TX_P0 0x3648
+#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK 0xffff
+#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK_POS 0
+#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_364C_AUX_TX_P0 0x364C
+#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK 0xf
+#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK_POS 0
+#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_3650_AUX_TX_P0 0x3650
+#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK 0xf000
+#define MCU_REQ_DATA_NUM_AUX_TX_P0_FLDMASK_POS 12
+#define MCU_REQUEST_DATA_NUM_AUX_TX_P0_FLDMASK_LEN 4
+
+#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK 0x200
+#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK_POS 9
+#define PHY_FIFO_RST_AUX_TX_P0_FLDMASK_LEN 1
+
+#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK 0x100
+#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0_FLDMASK_POS 8
+#define MCU_ACK_TRANSACTION_COMPLETE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TEST_CONFIG_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3654_AUX_TX_P0 0x3654
+#define TST_AUXRX_AUX_TX_P0_FLDMASK 0xff
+#define TST_AUXRX_AUX_TX_P0_FLDMASK_POS 0
+#define TST_AUXRX_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3658_AUX_TX_P0 0x3658
+#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK 0x1
+#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_OV_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK 0x2
+#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_TX_VALUE_SET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK 0x4
+#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK_POS 2
+#define AUX_TX_OEN_SET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK 0x8
+#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK_POS 3
+#define AUX_TX_OV_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_OFF_AUX_TX_P0_FLDMASK 0x10
+#define AUX_TX_OFF_AUX_TX_P0_FLDMASK_POS 4
+#define AUX_TX_OFF_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK 0x20
+#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK_POS 5
+#define EXT_AUX_PHY_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK 0x40
+#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK_POS 6
+#define EXT_TX_OEN_POLARITY_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK 0x80
+#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK_POS 7
+#define AUX_RX_OEN_SET_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_365C_AUX_TX_P0 0x365C
+#define AUX_RCTRL_AUX_TX_P0_FLDMASK 0x1f
+#define AUX_RCTRL_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RCTRL_AUX_TX_P0_FLDMASK_LEN 5
+
+#define AUX_RPD_AUX_TX_P0_FLDMASK 0x20
+#define AUX_RPD_AUX_TX_P0_FLDMASK_POS 5
+#define AUX_RPD_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_RX_SEL_AUX_TX_P0_FLDMASK 0x40
+#define AUX_RX_SEL_AUX_TX_P0_FLDMASK_POS 6
+#define AUX_RX_SEL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x80
+#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 7
+#define AUXRX_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x100
+#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 8
+#define AUXRXVALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK 0xe00
+#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK_POS 9
+#define AUX_DEBOUNCE_CLKSEL_AUX_TX_P0_FLDMASK_LEN 3
+
+#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK 0x1000
+#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_POS 12
+#define DATA_VALID_DEBOUNCE_SEL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3660_AUX_TX_P0 0x3660
+#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK 0xffff
+#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_INT_MASK_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_3664_AUX_TX_P0 0x3664
+#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK 0xffff
+#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_INT_FORCE_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_3668_AUX_TX_P0 0x3668
+#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK 0xffff
+#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK_POS 0
+#define DP_TX_INT_CLR_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_366C_AUX_TX_P0 0x366C
+#define XTAL_FREQ_AUX_TX_P0_FLDMASK 0xff00
+#define XTAL_FREQ_AUX_TX_P0_FLDMASK_POS 8
+#define XTAL_FREQ_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3670_AUX_TX_P0 0x3670
+#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK 0x7
+#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK_POS 0
+#define DPTX_GPIO_OEN_AUX_TX_P0_FLDMASK_LEN 3
+
+#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK 0x38
+#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK_POS 3
+#define DPTX_GPIO_OUT_AUX_TX_P0_FLDMASK_LEN 3
+
+#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK 0x1c0
+#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK_POS 6
+#define DPTX_GPIO_IN_AUX_TX_P0_FLDMASK_LEN 3
+
+#define AUX_IN_AUX_TX_P0_FLDMASK 0x200
+#define AUX_IN_AUX_TX_P0_FLDMASK_POS 9
+#define AUX_IN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK 0x400
+#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK_POS 10
+#define PD_AUX_RTERM_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK 0x7000
+#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK_POS 12
+#define DPTX_GPIO_EN_AUX_TX_P0_FLDMASK_LEN 3
+
+#define REG_3674_AUX_TX_P0 0x3674
+#define AUXTX_ISEL_AUX_TX_P0_FLDMASK 0x1f
+#define AUXTX_ISEL_AUX_TX_P0_FLDMASK_POS 0
+#define AUXTX_ISEL_AUX_TX_P0_FLDMASK_LEN 5
+
+#define AUXRX_VTH_AUX_TX_P0_FLDMASK 0x60
+#define AUXRX_VTH_AUX_TX_P0_FLDMASK_POS 5
+#define AUXRX_VTH_AUX_TX_P0_FLDMASK_LEN 2
+
+#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK 0x80
+#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK_POS 7
+#define EN_RXCM_BOOST_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK 0x1f00
+#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK_POS 8
+#define DPTX_AUX_R_CTRL_AUX_TX_P0_FLDMASK_LEN 5
+
+#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK 0x2000
+#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK_POS 13
+#define I2C_EN_AUXN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK 0x4000
+#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK_POS 14
+#define I2C_EN_AUXP_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3678_AUX_TX_P0 0x3678
+#define TEST_AUXTX_AUX_TX_P0_FLDMASK 0xff00
+#define TEST_AUXTX_AUX_TX_P0_FLDMASK_POS 8
+#define TEST_AUXTX_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_367C_AUX_TX_P0 0x367C
+#define DPTX_AUXRX_AUX_TX_P0_FLDMASK 0x4
+#define DPTX_AUXRX_AUX_TX_P0_FLDMASK_POS 2
+#define DPTX_AUXRX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK 0x8
+#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK_POS 3
+#define DPTX_AUXRX_VALID_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK 0x10
+#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK_POS 4
+#define DPTX_AUXRX_WO_TH_AUX_TX_P0_FLDMASK_LEN 1
+
+#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK 0x20
+#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK_POS 5
+#define DPTX_AUXRX_L_TEST_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_AUXRX_AUX_TX_P0_FLDMASK 0x400
+#define EN_AUXRX_AUX_TX_P0_FLDMASK_POS 10
+#define EN_AUXRX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_AUXTX_AUX_TX_P0_FLDMASK 0x800
+#define EN_AUXTX_AUX_TX_P0_FLDMASK_POS 11
+#define EN_AUXTX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_AUX_AUX_TX_P0_FLDMASK 0x1000
+#define EN_AUX_AUX_TX_P0_FLDMASK_POS 12
+#define EN_AUX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_5V_TOL_AUX_TX_P0_FLDMASK 0x2000
+#define EN_5V_TOL_AUX_TX_P0_FLDMASK_POS 13
+#define EN_5V_TOL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUXP_I_AUX_TX_P0_FLDMASK 0x4000
+#define AUXP_I_AUX_TX_P0_FLDMASK_POS 14
+#define AUXP_I_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUXN_I_AUX_TX_P0_FLDMASK 0x8000
+#define AUXN_I_AUX_TX_P0_FLDMASK_POS 15
+#define AUXN_I_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3680_AUX_TX_P0 0x3680
+#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK 0x1
+#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_SWAP_TX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3684_AUX_TX_P0 0x3684
+#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK 0x1f
+#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK_POS 0
+#define TEST_IO_LOOPBK_AUX_TX_P0_FLDMASK_LEN 5
+
+#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK 0x300
+#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK_POS 8
+#define RO_IO_LOOPBKT_AUX_TX_P0_FLDMASK_LEN 2
+
+#define SEL_TCLK_AUX_TX_P0_FLDMASK 0x3000
+#define SEL_TCLK_AUX_TX_P0_FLDMASK_POS 12
+#define SEL_TCLK_AUX_TX_P0_FLDMASK_LEN 2
+
+#define TESTEN_ASIO_AUX_TX_P0_FLDMASK 0x4000
+#define TESTEN_ASIO_AUX_TX_P0_FLDMASK_POS 14
+#define TESTEN_ASIO_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3688_AUX_TX_P0 0x3688
+#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK 0x7
+#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK_POS 0
+#define TEST_AUXRX_VTH_AUX_TX_P0_FLDMASK_LEN 3
+
+#define REG_368C_AUX_TX_P0 0x368C
+#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK 0x1
+#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK_POS 0
+#define RX_FIFO_DONE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK 0x2
+#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_POS 1
+#define RX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK 0x4
+#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK_POS 2
+#define TX_FIFO_DONE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK 0x8
+#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_POS 3
+#define TX_FIFO_DONE_CLR_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3690_AUX_TX_P0 0x3690
+#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK 0x7f
+#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK_POS 0
+#define DATA_LOW_CNT_THRD_AUX_TX_P0_FLDMASK_LEN 7
+
+#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK 0x100
+#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK_POS 8
+#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_36C0_AUX_TX_P0 0x36C0
+#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK 0xffff
+#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_POS 0
+#define RX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36C4_AUX_TX_P0 0x36C4
+#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK 0xffff
+#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_POS 0
+#define RX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36C8_AUX_TX_P0 0x36C8
+#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK 0x1
+#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK_POS 0
+#define RX_GTC_MASTER_REQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK 0x2
+#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_POS 1
+#define TX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK 0x4
+#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_POS 2
+#define RX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_36CC_AUX_TX_P0 0x36CC
+#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK 0xffff
+#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_POS 0
+#define RX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36D0_AUX_TX_P0 0x36D0
+#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK 0xffff
+#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_POS 0
+#define TX_GTC_VALUE_0_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36D4_AUX_TX_P0 0x36D4
+#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK 0xffff
+#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_POS 0
+#define TX_GTC_VALUE_1_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36D8_AUX_TX_P0 0x36D8
+#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK 0x1
+#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_POS 0
+#define RX_GTC_VALUE_PHASE_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK 0x2
+#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_POS 1
+#define TX_GTC_FREQ_LOCK_DONE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK 0x4
+#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK_POS 2
+#define TX_GTC_VALUE_PHASE_ADJUST_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_36DC_AUX_TX_P0 0x36DC
+#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK 0xffff
+#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_POS 0
+#define TX_GTC_PHASE_SKEW_OFFSET_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_36E0_AUX_TX_P0 0x36E0
+#define GTC_STATE_AUX_TX_P0_FLDMASK 0xf
+#define GTC_STATE_AUX_TX_P0_FLDMASK_POS 0
+#define GTC_STATE_AUX_TX_P0_FLDMASK_LEN 4
+
+#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK 0xf0
+#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK_POS 4
+#define RX_MASTER_LOCK_ACCQUI_CHKTIME_AUX_TX_P0_FLDMASK_LEN 4
+
+#define FREQ_AUX_TX_P0_FLDMASK 0xff00
+#define FREQ_AUX_TX_P0_FLDMASK_POS 8
+#define FREQ_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_36E4_AUX_TX_P0 0x36E4
+#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK 0x3ff
+#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK_POS 0
+#define GTC_TX_1M_ADD_VAL_AUX_TX_P0_FLDMASK_LEN 10
+
+#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK 0xf000
+#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK_POS 12
+#define GTC_TX_10M_ADD_VAL_AUX_TX_P0_FLDMASK_LEN 4
+
+#define REG_36E8_AUX_TX_P0 0x36E8
+#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK 0x1
+#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK_POS 0
+#define CHK_TX_PH_ADJUST_CHK_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK 0x2
+#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK_POS 1
+#define TX_SLAVE_WAIT_SKEW_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK 0x4
+#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK_POS 2
+#define GTC_SEND_RCV_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK 0x8
+#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK_POS 3
+#define AUXTX_HW_ACCS_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK 0x10
+#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK_POS 4
+#define GTC_TX_MASTER_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK 0x20
+#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK_POS 5
+#define GTC_TX_SLAVE_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK 0xf00
+#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK_POS 8
+#define OFFSET_TRY_NUM_AUX_TX_P0_FLDMASK_LEN 4
+
+#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK 0xc000
+#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK_POS 14
+#define HW_SW_ARBIT_AUX_TX_P0_FLDMASK_LEN 2
+
+#define REG_36EC_AUX_TX_P0 0x36EC
+#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK 0x7
+#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK_POS 0
+#define GTC_DB_OPTION_AUX_TX_P0_FLDMASK_LEN 3
+
+#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK 0x8
+#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK_POS 3
+#define TX_SLAVE_CHK_RX_LCK_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK 0xff00
+#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK_POS 8
+#define GTC_PUL_DELAY_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_36F0_AUX_TX_P0 0x36F0
+#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK 0x1f
+#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK_POS 0
+#define GTC_TX_LCK_ACQ_SEND_NUM_AUX_TX_P0_FLDMASK_LEN 5
+
+#define REG_3700_AUX_TX_P0 0x3700
+#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK 0x1
+#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_PHYWAKE_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK 0x2
+#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_PHYWAKE_ONLY_AUX_TX_P0_FLDMASK_LEN 1
+
+#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK 0x70
+#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK_POS 4
+#define PHYWAKE_PRE_NUM_AUX_TX_P0_FLDMASK_LEN 3
+
+#define REG_3704_AUX_TX_P0 0x3704
+#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK 0x1
+#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_PHYWAKE_ACK_RECV_COMPLETE_IRQ_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK 0x2
+#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK_POS 1
+#define AUX_TX_FIFO_WRITE_DATA_NEW_MODE_TOGGLE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK 0x4
+#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_POS 2
+#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3708_AUX_TX_P0 0x3708
+#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE0_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE1_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_370C_AUX_TX_P0 0x370C
+#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE2_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE3_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3710_AUX_TX_P0 0x3710
+#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE4_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE5_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3714_AUX_TX_P0 0x3714
+#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE6_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE7_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3718_AUX_TX_P0 0x3718
+#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE8_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE9_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_371C_AUX_TX_P0 0x371C
+#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE10_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE11_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3720_AUX_TX_P0 0x3720
+#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE12_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE13_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3724_AUX_TX_P0 0x3724
+#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK 0xff
+#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_TX_FIFO_WRITE_DATA_BYTE14_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_TX_FIFO_WRITE_DATA_BYTE15_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3740_AUX_TX_P0 0x3740
+#define HPD_OEN_AUX_TX_P0_FLDMASK 0x1
+#define HPD_OEN_AUX_TX_P0_FLDMASK_POS 0
+#define HPD_OEN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define HPD_I_AUX_TX_P0_FLDMASK 0x2
+#define HPD_I_AUX_TX_P0_FLDMASK_POS 1
+#define HPD_I_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_3744_AUX_TX_P0 0x3744
+#define TEST_AUXRX_AUX_TX_P0_FLDMASK 0xffff
+#define TEST_AUXRX_AUX_TX_P0_FLDMASK_POS 0
+#define TEST_AUXRX_AUX_TX_P0_FLDMASK_LEN 16
+
+#define REG_3748_AUX_TX_P0 0x3748
+#define CK_XTAL_AUX_TX_P0_FLDMASK 0x1
+#define CK_XTAL_AUX_TX_P0_FLDMASK_POS 0
+#define CK_XTAL_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_FT_MUX_AUX_TX_P0_FLDMASK 0x2
+#define EN_FT_MUX_AUX_TX_P0_FLDMASK_POS 1
+#define EN_FT_MUX_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_GPIO_AUX_TX_P0_FLDMASK 0x4
+#define EN_GPIO_AUX_TX_P0_FLDMASK_POS 2
+#define EN_GPIO_AUX_TX_P0_FLDMASK_LEN 1
+
+#define EN_HBR3_AUX_TX_P0_FLDMASK 0x8
+#define EN_HBR3_AUX_TX_P0_FLDMASK_POS 3
+#define EN_HBR3_AUX_TX_P0_FLDMASK_LEN 1
+
+#define PD_NGATE_OV_AUX_TX_P0_FLDMASK 0x10
+#define PD_NGATE_OV_AUX_TX_P0_FLDMASK_POS 4
+#define PD_NGATE_OV_AUX_TX_P0_FLDMASK_LEN 1
+
+#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK 0x20
+#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK_POS 5
+#define PD_NGATE_OVEN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define PD_VCM_OP_AUX_TX_P0_FLDMASK 0x40
+#define PD_VCM_OP_AUX_TX_P0_FLDMASK_POS 6
+#define PD_VCM_OP_AUX_TX_P0_FLDMASK_LEN 1
+
+#define CK_XTAL_SW_AUX_TX_P0_FLDMASK 0x80
+#define CK_XTAL_SW_AUX_TX_P0_FLDMASK_POS 7
+#define CK_XTAL_SW_AUX_TX_P0_FLDMASK_LEN 1
+
+#define SEL_FTMUX_AUX_TX_P0_FLDMASK 0x300
+#define SEL_FTMUX_AUX_TX_P0_FLDMASK_POS 8
+#define SEL_FTMUX_AUX_TX_P0_FLDMASK_LEN 2
+
+#define GTC_EN_AUX_TX_P0_FLDMASK 0x400
+#define GTC_EN_AUX_TX_P0_FLDMASK_POS 10
+#define GTC_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK 0x800
+#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK_POS 11
+#define GTC_DATA_IN_MODE_AUX_TX_P0_FLDMASK_LEN 1
+
+#define REG_374C_AUX_TX_P0 0x374C
+#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK 0xf
+#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_VALID_DB_TH_AUX_TX_P0_FLDMASK_LEN 4
+
+#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK 0x100
+#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK_POS 8
+#define CLK_AUX_MUX_VALID_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK 0x200
+#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK_POS 9
+#define CLK_AUX_MUX_VALID_INV_AUX_TX_P0_FLDMASK_LEN 1
+
+#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK 0xc00
+#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK_POS 10
+#define CLK_AUX_MUX_VALID_SEL_AUX_TX_P0_FLDMASK_LEN 2
+
+#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK 0x1000
+#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK_POS 12
+#define CLK_AUX_MUX_DATA_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK 0x2000
+#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK_POS 13
+#define CLK_AUX_MUX_DATA_INV_AUX_TX_P0_FLDMASK_LEN 1
+
+#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK 0xc000
+#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK_POS 14
+#define CLK_AUX_MUX_DATA_SEL_AUX_TX_P0_FLDMASK_LEN 2
+
+#define REG_3780_AUX_TX_P0 0x3780
+#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA0_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA1_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3784_AUX_TX_P0 0x3784
+#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA2_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA3_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3788_AUX_TX_P0 0x3788
+#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA4_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA5_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_378C_AUX_TX_P0 0x378C
+#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA6_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA7_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3790_AUX_TX_P0 0x3790
+#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA8_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA9_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3794_AUX_TX_P0 0x3794
+#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA10_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA11_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_3798_AUX_TX_P0 0x3798
+#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA12_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA13_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_379C_AUX_TX_P0 0x379C
+#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK 0xff
+#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_RX_FIFO_DATA14_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_RX_FIFO_DATA15_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_37C0_AUX_TX_P0 0x37C0
+#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK 0x1f
+#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_DRV_EN_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 5
+
+#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK 0x1f00
+#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_DRV_DIS_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 5
+
+#define REG_37C4_AUX_TX_P0 0x37C4
+#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK 0xff
+#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK_POS 0
+#define AUX_WAIT_TRANSFER_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 8
+
+#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK 0xff00
+#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK_POS 8
+#define AUX_WAIT_RECEIVE_TIME_THRD_AUX_TX_P0_FLDMASK_LEN 8
+
+#define REG_37C8_AUX_TX_P0 0x37C8
+#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK 0x1
+#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK_POS 0
+#define MTK_ATOP_EN_AUX_TX_P0_FLDMASK_LEN 1
+
+/*-----------------------------------------------------*/
+#define DP_TX_TOP_PWR_STATE (TOP_OFFSET + 0x00)
+#define DP_PWR_STATE_FLDMASK 0x3
+#define DP_PWR_STATE_FLDMASK_POS 0
+#define DP_PWR_STATE_FLDMASK_LEN 2
+
+#define DP_SCRAMB_EN_FLDMASK 0x4
+#define DP_SCRAMB_EN_FLDMASK_POS 2
+#define DP_SCRAMB_EN_FLDMASK_LEN 1
+
+#define DP_DISP_RST_FLDMASK 0x8
+#define DP_DISP_RST_FLDMASK_POS 3
+#define DP_DISP_RST_FLDMASK_LEN 1
+
+#define DP_TX_TOP_SWING_EMP (TOP_OFFSET + 0x04)
+#define DP_TX0_VOLT_SWING_FLDMASK 0x3
+#define DP_TX0_VOLT_SWING_FLDMASK_POS 0
+#define DP_TX0_VOLT_SWING_FLDMASK_LEN 2
+
+#define DP_TX0_PRE_EMPH_FLDMASK 0xc
+#define DP_TX0_PRE_EMPH_FLDMASK_POS 2
+#define DP_TX0_PRE_EMPH_FLDMASK_LEN 2
+
+#define DP_TX0_DATAK_FLDMASK 0xf0
+#define DP_TX0_DATAK_FLDMASK_POS 4
+#define DP_TX0_DATAK_FLDMASK_LEN 4
+
+#define DP_TX1_VOLT_SWING_FLDMASK 0x300
+#define DP_TX1_VOLT_SWING_FLDMASK_POS 8
+#define DP_TX1_VOLT_SWING_FLDMASK_LEN 2
+
+#define DP_TX1_PRE_EMPH_FLDMASK 0xc00
+#define DP_TX1_PRE_EMPH_FLDMASK_POS 10
+#define DP_TX1_PRE_EMPH_FLDMASK_LEN 2
+
+#define DP_TX1_DATAK_FLDMASK 0xf000
+#define DP_TX1_DATAK_FLDMASK_POS 12
+#define DP_TX1_DATAK_FLDMASK_LEN 4
+
+#define DP_TX2_VOLT_SWING_FLDMASK 0x30000
+#define DP_TX2_VOLT_SWING_FLDMASK_POS 16
+#define DP_TX2_VOLT_SWING_FLDMASK_LEN 2
+
+#define DP_TX2_PRE_EMPH_FLDMASK 0xc0000
+#define DP_TX2_PRE_EMPH_FLDMASK_POS 18
+#define DP_TX2_PRE_EMPH_FLDMASK_LEN 2
+
+#define DP_TX2_DATAK_FLDMASK 0xf00000
+#define DP_TX2_DATAK_FLDMASK_POS 20
+#define DP_TX2_DATAK_FLDMASK_LEN 4
+
+#define DP_TX3_VOLT_SWING_FLDMASK 0x3000000
+#define DP_TX3_VOLT_SWING_FLDMASK_POS 24
+#define DP_TX3_VOLT_SWING_FLDMASK_LEN 2
+
+#define DP_TX3_PRE_EMPH_FLDMASK 0xc000000
+#define DP_TX3_PRE_EMPH_FLDMASK_POS 26
+#define DP_TX3_PRE_EMPH_FLDMASK_LEN 2
+
+#define DP_TX3_DATAK_FLDMASK 0xf0000000L
+#define DP_TX3_DATAK_FLDMASK_POS 28
+#define DP_TX3_DATAK_FLDMASK_LEN 4
+
+#define DP_TX_TOP_APB_WSTRB (TOP_OFFSET + 0x10)
+#define APB_WSTRB_FLDMASK 0xf
+#define APB_WSTRB_FLDMASK_POS 0
+#define APB_WSTRB_FLDMASK_LEN 4
+
+#define APB_WSTRB_EN_FLDMASK 0x10
+#define APB_WSTRB_EN_FLDMASK_POS 4
+#define APB_WSTRB_EN_FLDMASK_LEN 1
+
+#define DP_TX_TOP_RESERVED (TOP_OFFSET + 0x14)
+#define RESERVED_FLDMASK 0xffffffffL
+#define RESERVED_FLDMASK_POS 0
+#define RESERVED_FLDMASK_LEN 32
+
+#define DP_TX_TOP_RESET_AND_PROBE (TOP_OFFSET + 0x20)
+#define SW_RST_B_FLDMASK 0x1f
+#define SW_RST_B_FLDMASK_POS 0
+#define SW_RST_B_FLDMASK_LEN 5
+
+#define PROBE_LOW_SEL_FLDMASK 0x38000
+#define PROBE_LOW_SEL_FLDMASK_POS 15
+#define PROBE_LOW_SEL_FLDMASK_LEN 3
+
+#define PROBE_HIGH_SEL_FLDMASK 0x1c0000
+#define PROBE_HIGH_SEL_FLDMASK_POS 18
+#define PROBE_HIGH_SEL_FLDMASK_LEN 3
+
+#define PROBE_LOW_HIGH_SWAP_FLDMASK 0x200000
+#define PROBE_LOW_HIGH_SWAP_FLDMASK_POS 21
+#define PROBE_LOW_HIGH_SWAP_FLDMASK_LEN 1
+
+#define DP_TX_TOP_SOFT_PROBE (TOP_OFFSET + 0x24)
+#define SW_PROBE_VALUE_FLDMASK 0xffffffffL
+#define SW_PROBE_VALUE_FLDMASK_POS 0
+#define SW_PROBE_VALUE_FLDMASK_LEN 32
+
+#define DP_TX_TOP_IRQ_STATUS (TOP_OFFSET + 0x28)
+#define RGS_IRQ_STATUS_FLDMASK 0x7
+#define RGS_IRQ_STATUS_FLDMASK_POS 0
+#define RGS_IRQ_STATUS_FLDMASK_LEN 3
+
+#define DP_TX_TOP_IRQ_MASK (TOP_OFFSET + 0x2C)
+#define IRQ_MASK_FLDMASK 0x7
+#define IRQ_MASK_FLDMASK_POS 0
+#define IRQ_MASK_FLDMASK_LEN 3
+
+#define IRQ_OUT_HIGH_ACTIVE_FLDMASK 0x100
+#define IRQ_OUT_HIGH_ACTIVE_FLDMASK_POS 8
+#define IRQ_OUT_HIGH_ACTIVE_FLDMASK_LEN 1
+
+#define DP_TX_TOP_BLACK_SCREEN (TOP_OFFSET + 0x30)
+#define BLACK_SCREEN_ENABLE_FLDMASK 0x1
+#define BLACK_SCREEN_ENABLE_FLDMASK_POS 0
+#define BLACK_SCREEN_ENABLE_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_PD (TOP_OFFSET + 0x38)
+#define MEM_ISO_EN_FLDMASK 0x1
+#define MEM_ISO_EN_FLDMASK_POS 0
+#define MEM_ISO_EN_FLDMASK_LEN 1
+
+#define MEM_PD_FLDMASK 0x2
+#define MEM_PD_FLDMASK_POS 1
+#define MEM_PD_FLDMASK_LEN 1
+
+#define FUSE_SEL_FLDMASK 0x4
+#define FUSE_SEL_FLDMASK_POS 2
+#define FUSE_SEL_FLDMASK_LEN 1
+
+#define LOAD_PREFUSE_FLDMASK 0x8
+#define LOAD_PREFUSE_FLDMASK_POS 3
+#define LOAD_PREFUSE_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MBIST_PREFUSE (TOP_OFFSET + 0x3C)
+#define RGS_PREFUSE_FLDMASK 0xffff
+#define RGS_PREFUSE_FLDMASK_POS 0
+#define RGS_PREFUSE_FLDMASK_LEN 16
+
+#define DP_TX_TOP_MEM_DELSEL_0 (TOP_OFFSET + 0x40)
+#define DELSEL_0_FLDMASK 0xfffff
+#define DELSEL_0_FLDMASK_POS 0
+#define DELSEL_0_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_0_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_0_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_0_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_1 (TOP_OFFSET + 0x44)
+#define DELSEL_1_FLDMASK 0xfffff
+#define DELSEL_1_FLDMASK_POS 0
+#define DELSEL_1_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_1_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_1_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_1_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_2 (TOP_OFFSET + 0x48)
+#define DELSEL_2_FLDMASK 0xfffff
+#define DELSEL_2_FLDMASK_POS 0
+#define DELSEL_2_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_2_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_2_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_2_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_3 (TOP_OFFSET + 0x4C)
+#define DELSEL_3_FLDMASK 0xfffff
+#define DELSEL_3_FLDMASK_POS 0
+#define DELSEL_3_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_3_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_3_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_3_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_4 (TOP_OFFSET + 0x50)
+#define DELSEL_4_FLDMASK 0xfffff
+#define DELSEL_4_FLDMASK_POS 0
+#define DELSEL_4_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_4_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_4_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_4_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_5 (TOP_OFFSET + 0x54)
+#define DELSEL_5_FLDMASK 0xfffff
+#define DELSEL_5_FLDMASK_POS 0
+#define DELSEL_5_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_5_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_5_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_5_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_6 (TOP_OFFSET + 0x58)
+#define DELSEL_6_FLDMASK 0xfffff
+#define DELSEL_6_FLDMASK_POS 0
+#define DELSEL_6_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_6_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_6_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_6_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_7 (TOP_OFFSET + 0x5C)
+#define DELSEL_7_FLDMASK 0xfffff
+#define DELSEL_7_FLDMASK_POS 0
+#define DELSEL_7_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_7_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_7_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_7_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_8 (TOP_OFFSET + 0x60)
+#define DELSEL_8_FLDMASK 0xfffff
+#define DELSEL_8_FLDMASK_POS 0
+#define DELSEL_8_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_8_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_8_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_8_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_9 (TOP_OFFSET + 0x64)
+#define DELSEL_9_FLDMASK 0xfffff
+#define DELSEL_9_FLDMASK_POS 0
+#define DELSEL_9_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_9_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_9_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_9_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_10 (TOP_OFFSET + 0x68)
+#define DELSEL_10_FLDMASK 0xfffff
+#define DELSEL_10_FLDMASK_POS 0
+#define DELSEL_10_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_10_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_10_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_10_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_11 (TOP_OFFSET + 0x6C)
+#define DELSEL_11_FLDMASK 0xfffff
+#define DELSEL_11_FLDMASK_POS 0
+#define DELSEL_11_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_11_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_11_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_11_FLDMASK_LEN 1
+
+#define DP_TX_TOP_MEM_DELSEL_12 (TOP_OFFSET + 0x70)
+#define DELSEL_12_FLDMASK 0xfffff
+#define DELSEL_12_FLDMASK_POS 0
+#define DELSEL_12_FLDMASK_LEN 20
+
+#define USE_DEFAULT_DELSEL_12_FLDMASK 0x100000
+#define USE_DEFAULT_DELSEL_12_FLDMASK_POS 20
+#define USE_DEFAULT_DELSEL_12_FLDMASK_LEN 1
+
+#define DP_TX_TOP_PWR_ACK (TOP_OFFSET + 0x80)
+#define RGS_DP_TX_PWR_ACK_FLDMASK 0x1
+#define RGS_DP_TX_PWR_ACK_FLDMASK_POS 0
+#define RGS_DP_TX_PWR_ACK_FLDMASK_LEN 1
+
+#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK 0x2
+#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK_POS 1
+#define RGS_DP_TX_PWR_ACK_2ND_FLDMASK_LEN 1
+
+#define DP_TX_SECURE_REG0 (SEC_OFFSET + 0x00)
+#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK 0xffffffffL
+#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK_POS 0
+#define HDCP22_KS_XOR_LC128_KEY_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG1 (SEC_OFFSET + 0x04)
+#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK 0xffffffffL
+#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK_POS 0
+#define HDCP22_KS_XOR_LC128_KEY_1_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG2 (SEC_OFFSET + 0x08)
+#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK 0xffffffffL
+#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK_POS 0
+#define HDCP22_KS_XOR_LC128_KEY_2_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG3 (SEC_OFFSET + 0x0c)
+#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK 0xffffffffL
+#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK_POS 0
+#define HDCP22_KS_XOR_LC128_KEY_3_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG4 (SEC_OFFSET + 0x10)
+#define HDCP22_RIV_0_FLDMASK 0xffffffffL
+#define HDCP22_RIV_0_FLDMASK_POS 0
+#define HDCP22_RIV_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG5 (SEC_OFFSET + 0x14)
+#define HDCP22_RIV_1_FLDMASK 0xffffffffL
+#define HDCP22_RIV_1_FLDMASK_POS 0
+#define HDCP22_RIV_1_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG6 (SEC_OFFSET + 0x18)
+#define HDCP13_LN_SEED_FLDMASK 0xff
+#define HDCP13_LN_SEED_FLDMASK_POS 0
+#define HDCP13_LN_SEED_FLDMASK_LEN 8
+
+#define DP_TX_SECURE_REG7 (SEC_OFFSET + 0x1C)
+#define HDCP13_LN_CODE_0_FLDMASK 0xffffffffL
+#define HDCP13_LN_CODE_0_FLDMASK_POS 0
+#define HDCP13_LN_CODE_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG8 (SEC_OFFSET + 0x20)
+#define HDCP13_LN_CODE_1_FLDMASK 0xffffff
+#define HDCP13_LN_CODE_1_FLDMASK_POS 0
+#define HDCP13_LN_CODE_1_FLDMASK_LEN 24
+
+#define DP_TX_SECURE_REG9 (SEC_OFFSET + 0x24)
+#define HDCP13_AN_CODE_0_FLDMASK 0xffffffffL
+#define HDCP13_AN_CODE_0_FLDMASK_POS 0
+#define HDCP13_AN_CODE_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG10 (SEC_OFFSET + 0x28)
+#define HDCP13_AN_CODE_1_FLDMASK 0xffffffffL
+#define HDCP13_AN_CODE_1_FLDMASK_POS 0
+#define HDCP13_AN_CODE_1_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_REG11 (SEC_OFFSET + 0x2C)
+#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK 0x1
+#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK_POS 0
+#define DP_TX_TRANSMITTER_4P_RESET_SW_SECURE_FLDMASK_LEN 1
+
+#define HDCP22_RST_SW_SECURE_FLDMASK 0x2
+#define HDCP22_RST_SW_SECURE_FLDMASK_POS 1
+#define HDCP22_RST_SW_SECURE_FLDMASK_LEN 1
+
+#define HDCP13_RST_SW_SECURE_FLDMASK 0x4
+#define HDCP13_RST_SW_SECURE_FLDMASK_POS 2
+#define HDCP13_RST_SW_SECURE_FLDMASK_LEN 1
+
+#define VIDEO_MUTE_SW_SECURE_FLDMASK 0x8
+#define VIDEO_MUTE_SW_SECURE_FLDMASK_POS 3
+#define VIDEO_MUTE_SW_SECURE_FLDMASK_LEN 1
+
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK 0x10
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK_POS 4
+#define VIDEO_MUTE_SEL_SECURE_FLDMASK_LEN 1
+
+#define HDCP_FRAME_EN_SECURE_FLDMASK 0x20
+#define HDCP_FRAME_EN_SECURE_FLDMASK_POS 5
+#define HDCP_FRAME_EN_SECURE_FLDMASK_LEN 1
+
+#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK 0x40
+#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK_POS 6
+#define HDCP_FRAME_EN_SEL_SECURE_FLDMASK_LEN 1
+
+#define VSC_SEL_SECURE_FLDMASK 0x80
+#define VSC_SEL_SECURE_FLDMASK_POS 7
+#define VSC_SEL_SECURE_FLDMASK_LEN 1
+
+#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK 0x100
+#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK_POS 8
+#define VSC_DATA_TOGGLE_VESA_SECURE_FLDMASK_LEN 1
+
+#define VSC_DATA_RDY_VESA_SECURE_FLDMASK 0x200
+#define VSC_DATA_RDY_VESA_SECURE_FLDMASK_POS 9
+#define VSC_DATA_RDY_VESA_SECURE_FLDMASK_LEN 1
+
+#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK 0x400
+#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK_POS 10
+#define VSC_DATA_TOGGLE_CEA_SECURE_FLDMASK_LEN 1
+
+#define VSC_DATA_RDY_CEA_SECURE_FLDMASK 0x800
+#define VSC_DATA_RDY_CEA_SECURE_FLDMASK_POS 11
+#define VSC_DATA_RDY_CEA_SECURE_FLDMASK_LEN 1
+
+#define DP_TX_SECURE_REG12 (SEC_OFFSET + 0x30)
+#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK 0xff000000L
+#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK_POS 24
+#define VSC_DATA_BYTE7_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK 0xff0000
+#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK_POS 16
+#define VSC_DATA_BYTE6_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK 0xff00
+#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK_POS 8
+#define VSC_DATA_BYTE5_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK 0xff
+#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK_POS 0
+#define VSC_DATA_BYTE4_CEA_SECURE_FLDMASK_LEN 8
+
+#define DP_TX_SECURE_REG13 (SEC_OFFSET + 0x34)
+#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK 0xff000000L
+#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK_POS 24
+#define VSC_DATA_BYTE3_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK 0xff0000
+#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK_POS 16
+#define VSC_DATA_BYTE2_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK 0xff00
+#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK_POS 8
+#define VSC_DATA_BYTE1_CEA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK 0xff
+#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK_POS 0
+#define VSC_DATA_BYTE0_CEA_SECURE_FLDMASK_LEN 8
+
+#define DP_TX_SECURE_REG14 (SEC_OFFSET + 0x38)
+#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK 0xff000000L
+#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK_POS 24
+#define VSC_DATA_BYTE7_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK 0xff0000
+#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK_POS 16
+#define VSC_DATA_BYTE6_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK 0xff00
+#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK_POS 8
+#define VSC_DATA_BYTE5_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK 0xff
+#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK_POS 0
+#define VSC_DATA_BYTE4_VESA_SECURE_FLDMASK_LEN 8
+
+#define DP_TX_SECURE_REG15 (SEC_OFFSET + 0x3C)
+#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK 0xff000000L
+#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK_POS 24
+#define VSC_DATA_BYTE3_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK 0xff0000
+#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK_POS 16
+#define VSC_DATA_BYTE2_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK 0xff00
+#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK_POS 8
+#define VSC_DATA_BYTE1_VESA_SECURE_FLDMASK_LEN 8
+
+#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK 0xff
+#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK_POS 0
+#define VSC_DATA_BYTE0_VESA_SECURE_FLDMASK_LEN 8
+
+#define DP_TX_SECURE_STATUS_0 (SEC_OFFSET + 0x80)
+#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK 0xffffffffL
+#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK_POS 0
+#define RGS_DP_TX_HDCP13_HDCP_AN_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_STATUS_1 (SEC_OFFSET + 0x84)
+#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK 0xffffffffL
+#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK_POS 0
+#define RGS_DP_TX_HDCP13_HDCP_AN_1_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_STATUS_2 (SEC_OFFSET + 0x88)
+#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK 0xffff
+#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK_POS 0
+#define RGS_DP_TX_HDCP13_HDCP_R0_FLDMASK_LEN 16
+
+#define DP_TX_SECURE_STATUS_3 (SEC_OFFSET + 0x8C)
+#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK 0xffffffffL
+#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK_POS 0
+#define RGS_DP_TX_HDCP13_HDCP_M0_0_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_STATUS_4 (SEC_OFFSET + 0x90)
+#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK 0xffffffffL
+#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK_POS 0
+#define RGS_DP_TX_HDCP13_HDCP_M0_1_FLDMASK_LEN 32
+
+#define DP_TX_SECURE_ACC_FAIL (SEC_OFFSET + 0xf0)
+#define NO_AUTH_READ_VALUE_FLDMASK 0xffffffffL
+#define NO_AUTH_READ_VALUE_FLDMASK_POS 0
+#define NO_AUTH_READ_VALUE_FLDMASK_LEN 32
+
+#define DPCD_00000 0x00000
+#define DPCD_00001 0x00001
+#define DPCD_00002 0x00002
+#define DPCD_00003 0x00003
+#define DPCD_00004 0x00004
+#define DPCD_00005 0x00005
+#define DPCD_0000A 0x0000A
+#define DPCD_0000E 0x0000E
+#define DPCD_00021 0x00021
+#define DPCD_00030 0x00030
+#define DPCD_00060 0x00060
+#define DPCD_00080 0x00080
+#define DPCD_00090 0x00090
+#define DPCD_00100 0x00100
+#define DPCD_00101 0x00101
+#define DPCD_00102 0x00102
+#define DPCD_00103 0x00103
+#define DPCD_00104 0x00104
+#define DPCD_00105 0x00105
+#define DPCD_00106 0x00106
+#define DPCD_00107 0x00107
+#define DPCD_00111 0x00111
+#define DPCD_00120 0x00120
+#define DPCD_00160 0x00160
+#define DPCD_001A1 0x001A1
+#define DPCD_001C0 0x001C0
+#define DPCD_00200 0x00200
+#define DPCD_00201 0x00201
+#define DPCD_00202 0x00202
+#define DPCD_00203 0x00203
+#define DPCD_00204 0x00204
+#define DPCD_00205 0x00205
+#define DPCD_00206 0x00206
+#define DPCD_00210 0x00210
+#define DPCD_00218 0x00218
+#define DPCD_00219 0x00219
+#define DPCD_00220 0x00220
+#define DPCD_00230 0x00230
+#define DPCD_00250 0x00250
+#define DPCD_00260 0x00260
+#define DPCD_00261 0x00261
+#define DPCD_00271 0x00271
+#define DPCD_00280 0x00280
+#define DPCD_00281 0x00281
+#define DPCD_00282 0x00282
+#define DPCD_002C0 0x002C0
+#define DPCD_00600 0x00600
+#define DPCD_01000 0x01000
+#define DPCD_01200 0x01200
+#define DPCD_01400 0x01400
+#define DPCD_01600 0x01600
+#define DPCD_02002 0x02002
+#define DPCD_02003 0x02003
+#define DPCD_0200C 0x0200C
+#define DPCD_0200D 0x0200D
+#define DPCD_0200E 0x0200E
+#define DPCD_0200F 0x0200F
+#define DPCD_02200 0x02200
+#define DPCD_02201 0x02201
+#define DPCD_02202 0x02202
+#define DPCD_02203 0x02203
+#define DPCD_02204 0x02204
+#define DPCD_02205 0x02205
+#define DPCD_02206 0x02206
+#define DPCD_02207 0x02207
+#define DPCD_02208 0x02208
+#define DPCD_02209 0x02209
+#define DPCD_0220A 0x0220A
+#define DPCD_0220B 0x0220B
+#define DPCD_0220C 0x0220C
+#define DPCD_0220D 0x0220D
+#define DPCD_0220E 0x0220E
+#define DPCD_0220F 0x0220F
+#define DPCD_02210 0x02210
+#define DPCD_02211 0x02211
+#define DPCD_68000 0x68000
+#define DPCD_68005 0x68005
+#define DPCD_68007 0x68007
+#define DPCD_6800C 0x6800C
+#define DPCD_68014 0x68014
+#define DPCD_68018 0x68018
+#define DPCD_6801C 0x6801C
+#define DPCD_68020 0x68020
+#define DPCD_68024 0x68024
+#define DPCD_68028 0x68028
+#define DPCD_68029 0x68029
+#define DPCD_6802A 0x6802A
+#define DPCD_6802C 0x6802C
+#define DPCD_6803B 0x6803B
+#define DPCD_6921D 0x6921D
+#define DPCD_69000 0x69000
+#define DPCD_69008 0x69008
+#define DPCD_6900B 0x6900B
+#define DPCD_69215 0x69215
+#define DPCD_6921D 0x6921D
+#define DPCD_69220 0x69220
+#define DPCD_692A0 0x692A0
+#define DPCD_692B0 0x692B0
+#define DPCD_692C0 0x692C0
+#define DPCD_692E0 0x692E0
+#define DPCD_692F0 0x692F0
+#define DPCD_692F8 0x692F8
+#define DPCD_69318 0x69318
+#define DPCD_69328 0x69328
+#define DPCD_69330 0x69330
+#define DPCD_69332 0x69332
+#define DPCD_69335 0x69335
+#define DPCD_69345 0x69345
+#define DPCD_693E0 0x693E0
+#define DPCD_693F0 0x693F0
+#define DPCD_693F3 0x693F3
+#define DPCD_693F5 0x693F5
+#define DPCD_69473 0x69473
+#define DPCD_69493 0x69493
+#define DPCD_69494 0x69494
+#define DPCD_69518 0x69518
+
+#endif /* SOC_MEDIATEK_MT8195_DRTX_REG_H */