commit 55d0f40734e64e38c1a46b96266daf468c5efad6
author Elyes Haouas <ehaouas@noos.fr> Sat Jul 16 09:53:05 2022 +0200
committer Martin L Roth <gaumless@tutanota.com> Sun Jul 17 22:03:37 2022 +0000
tree 9848a1b1ab916e30d296e9811b8ec3af986b2c33
parent ab304bc091b793b52cd5a8d1255e6e144727451a

soc/amd: Fix some white spaces issues

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ibe20d48bdd8c776f9658620a13814f96e564dabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/amd/cezanne/agesa_acpi.c

diff --git a/src/soc/amd/cezanne/agesa_acpi.c b/src/soc/amd/cezanne/agesa_acpi.c
index 47ca5f2..a397360 100644
--- a/src/soc/amd/cezanne/agesa_acpi.c
+++ b/src/soc/amd/cezanne/agesa_acpi.c
@@ -17,7 +17,7 @@
 
 	/* IVRS */
 	current = ALIGN(current, 8);
-	ivrs = (acpi_ivrs_t *) current;
+	ivrs = (acpi_ivrs_t *)current;
 	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
 	current += ivrs->header.length;
 	acpi_add_table(rsdp, ivrs);

src/soc/amd/picasso/agesa_acpi.c

diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c
index db95b92..e4a9b14 100644
--- a/src/soc/amd/picasso/agesa_acpi.c
+++ b/src/soc/amd/picasso/agesa_acpi.c
@@ -558,7 +558,7 @@
 
 	/* IVRS */
 	current = ALIGN(current, 8);
-	ivrs = (acpi_ivrs_t *) current;
+	ivrs = (acpi_ivrs_t *)current;
 	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
 	current += ivrs->header.length;
 	acpi_add_table(rsdp, ivrs);

src/soc/amd/sabrina/agesa_acpi.c

diff --git a/src/soc/amd/sabrina/agesa_acpi.c b/src/soc/amd/sabrina/agesa_acpi.c
index f8193c7..9062c7a 100644
--- a/src/soc/amd/sabrina/agesa_acpi.c
+++ b/src/soc/amd/sabrina/agesa_acpi.c
@@ -19,7 +19,7 @@
 
 	/* IVRS */
 	current = ALIGN(current, 8);
-	ivrs = (acpi_ivrs_t *) current;
+	ivrs = (acpi_ivrs_t *)current;
 	acpi_create_ivrs(ivrs, acpi_fill_ivrs);
 	current += ivrs->header.length;
 	acpi_add_table(rsdp, ivrs);

src/soc/amd/stoneyridge/memmap.c

diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c
index f7c6b00..f015740 100644
--- a/src/soc/amd/stoneyridge/memmap.c
+++ b/src/soc/amd/stoneyridge/memmap.c
@@ -21,7 +21,7 @@
 
 	/* 8MB alignment to keep MTRR usage low */
 	return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()
-				  - CONFIG_SMM_TSEG_SIZE, 8*MiB);
+				  - CONFIG_SMM_TSEG_SIZE, 8 * MiB);
 }
 
 static uintptr_t smm_region_start(void)

src/soc/amd/stoneyridge/northbridge.c

diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index a47ef25..500940c 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -110,7 +110,7 @@
 	link_num = IOINDEX_LINK(res->index);
 
 	if (res->flags & IORESOURCE_IO)
-		set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
+		set_io_addr_reg(dev, nodeid, link_num, reg, rbase >> 8, rend >> 8);
 	else if (res->flags & IORESOURCE_MEM)
 		set_mmio_addr_reg(nodeid, link_num, reg,
 				(res->index >> 24), rbase >> 8, rend >> 8);

src/soc/amd/stoneyridge/smbus_spd.c

diff --git a/src/soc/amd/stoneyridge/smbus_spd.c b/src/soc/amd/stoneyridge/smbus_spd.c
index 773aad1..1f83448 100644
--- a/src/soc/amd/stoneyridge/smbus_spd.c
+++ b/src/soc/amd/stoneyridge/smbus_spd.c
@@ -39,7 +39,7 @@
 		printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
 		return error;
 	}
-	*pbuf = (char) error;
+	*pbuf = (char)error;
 	pbuf++;
 
 	/* Read the remaining SPD bytes using do_smbus_recv_byte for speed */
@@ -49,7 +49,7 @@
 			printk(BIOS_ERR, "-------------SPD READ ERROR-----------\n");
 			return error;
 		}
-		*pbuf = (char) error;
+		*pbuf = (char)error;
 		pbuf++;
 	}
 	printk(BIOS_SPEW, "\n");