tree 71961e4cdcebe0c412ee6add95a7045b030138dd
parent b486fe95bf455008d5d5c6df7e1c1fc836e9ccd1
author Subrata Banik <subratabanik@google.com> 1673855687 +0530
committer Felix Held <felix-coreboot@felixheld.de> 1673983513 +0000

soc/intel/alderlake: Avoid redundant chipset programming in romstage

This patch refactors the mainboard_romstage_entry() function to avoid
redundant chipset programming caused by global reset due to CSE FW
sync operation. Hence, keeping only the minimal and mandatory
operations required to perform CSE FW sync successfully.

This would help to optimize the boot flow by removing redundant
programming like SA, SMBUS twice in every CSE FW update path.

TEST=Able to build and boot Google/Marasov successfully.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>