soc/intel/alderlake: Correct GPE DWx assignment as per EDS
List of changes:
1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG
register per GPIO Community.
2. PMC_GPP_* macros are also updated as per GPIO_CFG register
in PMC space.
BUG=b:183464235
TEST=Able to fix the TPM IRQ issue on SM.
Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c
index f0db5e9..1f96179 100644
--- a/src/soc/intel/alderlake/gpio.c
+++ b/src/soc/intel/alderlake/gpio.c
@@ -178,10 +178,8 @@
{ PMC_GPD, GPD },
{ PMC_GPP_C, GPP_C },
{ PMC_GPP_F, GPP_F },
- { PMC_GPP_HVMOS, GPP_HVMOS },
{ PMC_GPP_E, GPP_E },
{ PMC_GPP_R, GPP_R },
- { PMC_GPP_SPI0, GPP_SPI0 },
};
*num = ARRAY_SIZE(routes);
return routes;
diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
index bf95716..5035718 100644
--- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
+++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h
@@ -6,25 +6,21 @@
* Most of the fixed numbers and macros are based on the GPP groups.
* The GPIO groups are accessed through register blocks called
* communities.
+ *
+ * Refer to Alder Lake PCH EDS Chapter 27, MISCCFG register offset 0x10
+ * for each GPIO community to get GPIO group to GPE_DWx assignment.
*/
-/* GPIO COMM 0 */
#define GPP_B 0x0
#define GPP_T 0x1
#define GPP_A 0x2
-/* GPIO COMM 1 */
-#define GPP_S 0x3
-#define GPP_H 0x4
-#define GPP_D 0x5
-/* GPIO COMM 2 */
-#define GPD 0x6
-/* GPIO COMM 4 */
-#define GPP_C 0x7
-#define GPP_F 0x8
-#define GPP_HVMOS 0x9
-#define GPP_E 0xA
-/* GPIO COMM 5 */
-#define GPP_R 0xB
-#define GPP_SPI0 0xC
+#define GPP_R 0x3
+#define GPD 0x4
+#define GPP_S 0x5
+#define GPP_H 0x6
+#define GPP_D 0x7
+#define GPP_F 0xA
+#define GPP_C 0xB
+#define GPP_E 0xC
#define GPIO_MAX_NUM_PER_GROUP 26
diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h
index 8887d9b..a2a7540 100644
--- a/src/soc/intel/alderlake/include/soc/pmc.h
+++ b/src/soc/intel/alderlake/include/soc/pmc.h
@@ -133,16 +133,14 @@
#define PMC_GPP_B 0x0
#define PMC_GPP_T 0x1
#define PMC_GPP_A 0x2
-#define PMC_GPP_S 0x3
-#define PMC_GPP_H 0x4
-#define PMC_GPP_D 0x5
-#define PMC_GPD 0x6
-#define PMC_GPP_C 0x7
-#define PMC_GPP_F 0x8
-#define PMC_GPP_HVMOS 0x9
-#define PMC_GPP_E 0xA
-#define PMC_GPP_R 0xB
-#define PMC_GPP_SPI0 0xC
+#define PMC_GPP_R 0x3
+#define PMC_GPD 0x4
+#define PMC_GPP_S 0x5
+#define PMC_GPP_H 0x6
+#define PMC_GPP_D 0x7
+#define PMC_GPP_F 0xA
+#define PMC_GPP_C 0xB
+#define PMC_GPP_E 0xC
#define GBLRST_CAUSE0 0x1924
#define GBLRST_CAUSE0_THERMTRIP (1 << 5)