soc/intel/xeon_sp: Redesign resource allocation
The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- Handle IOAT stacks with multiple domains in soc-specific code
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c
index 193b859..e7ce5e3 100644
--- a/src/soc/intel/xeon_sp/spr/soc_acpi.c
+++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c
@@ -188,6 +188,9 @@
static void create_dsdt_dino_resource(uint8_t socket, uint8_t stack, const STACK_RES *ri, bool stack_enabled)
{
+ if (!stack_enabled)
+ return;
+
/*
Stacks 8 .. B (TYPE_DINO)
Scope: DI<socket><stack> for DINO, ResourceTemplate: DT
@@ -247,6 +250,11 @@
snprintf(tres, sizeof(tres), "HU%d%X", socket, stack);
}
+ /* Note, some SKU doesn't provide CPM1 and HQM1 and owns smaller bus ranges
+ accordingly*/
+ if (bus_limit > ri->BusLimit)
+ continue;
+
printk(BIOS_DEBUG,
"\tCreating Dino ResourceTemplate %s for socket: %d, "
"stack: %d\n bus_base:0x%x, bus_limit:0x%x\n",
@@ -255,30 +263,19 @@
acpigen_write_name(tres);
acpigen_write_resourcetemplate_header();
- if (stack_enabled) {
- acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
- (bus_limit - bus_base + 1));
+ acpigen_resource_word(2, 0xc, 0, 0, bus_base, bus_limit, 0x0,
+ (bus_limit - bus_base + 1));
- /* Mem32 resource */
- if (rlist[i] == DSDT_DINO)
- acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
- ri->PciResourceMem32Limit, 0x0,
- (ri->PciResourceMem32Limit
- - ri->PciResourceMem32Base + 1));
+ /* Mem32 resource */
+ if (rlist[i] == DSDT_DINO)
+ acpigen_resource_dword(0, 0xc, 1, 0, ri->PciResourceMem32Base,
+ ri->PciResourceMem32Limit, 0x0,
+ (ri->PciResourceMem32Limit
+ - ri->PciResourceMem32Base + 1));
- /* Mem64 resource */
- acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
- (mem64_limit - mem64_base + 1));
- } else {
- acpigen_resource_word(2, 0, 0, 0, 0, 0, 0, 0);
-
- /* Mem32 resource */
- if (rlist[i] == DSDT_DINO)
- acpigen_resource_dword(0, 0, 1, 0, 0, 0, 0, 0);
-
- /* Mem64 resource */
- acpigen_resource_qword(0, 0, 1, 0, 0, 0, 0, 0);
- }
+ /* Mem64 resource */
+ acpigen_resource_qword(0, 0xc, 1, 0, mem64_base, mem64_limit, 0,
+ (mem64_limit - mem64_base + 1));
acpigen_write_resourcetemplate_footer();
}