soc/intel/xeon_sp: Redesign resource allocation
The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FSP HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- Handle IOAT stacks with multiple domains in soc-specific code
TEST=intel/archercity CRB
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: Idb29c24b71a18e2e092f9d4953d106e6ca0a5fe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c
index dd9c113..39a7eba 100644
--- a/src/soc/intel/xeon_sp/cpx/chip.c
+++ b/src/soc/intel/xeon_sp/cpx/chip.c
@@ -36,9 +36,9 @@
#endif
static struct device_operations pci_domain_ops = {
- .read_resources = &pci_domain_read_resources,
- .set_resources = &xeonsp_pci_domain_set_resources,
- .scan_bus = &xeonsp_pci_domain_scan_bus,
+ .read_resources = iio_pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .scan_bus = iio_pci_domain_scan_bus,
#if CONFIG(HAVE_ACPI_TABLES)
.write_acpi_tables = &northbridge_write_acpi_tables,
.acpi_name = soc_acpi_name
diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c
index 64efb61..e277752 100644
--- a/src/soc/intel/xeon_sp/cpx/soc_util.c
+++ b/src/soc/intel/xeon_sp/cpx/soc_util.c
@@ -25,11 +25,16 @@
return *memmap_addr;
}
-bool is_iio_stack_res(const STACK_RES *res)
+bool stack_needs_resource_alloc(const STACK_RES *res)
{
return res->Personality == TYPE_UBOX_IIO;
}
+bool is_pcie_iio_stack_res(const STACK_RES *res)
+{
+ return stack_needs_resource_alloc(res);
+}
+
uint8_t get_stack_busno(const uint8_t stack)
{
if (stack >= MAX_IIO_STACK) {