Change all clrsetbits_leXX() to clrsetbitsXX()
This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
diff --git a/src/soc/nvidia/tegra210/addressmap.c b/src/soc/nvidia/tegra210/addressmap.c
index 716c900..60ca16c 100644
--- a/src/soc/nvidia/tegra210/addressmap.c
+++ b/src/soc/nvidia/tegra210/addressmap.c
@@ -297,14 +297,14 @@
write32(&mc->security_carveout2_bom_hi, 0);
/* Set the locked bit. This will lock out any other writes! */
- setbits_le32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
+ setbits32(&mc->security_carveout2_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
/* Set the carveout3 base to 0, unused */
write32(&mc->security_carveout3_bom, 0);
write32(&mc->security_carveout3_bom_hi, 0);
/* Set the locked bit. This will lock out any other writes! */
- setbits_le32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
+ setbits32(&mc->security_carveout3_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
}
void nvdec_region_init(void)
@@ -322,7 +322,7 @@
write32(&mc->security_carveout1_bom_hi, 0);
/* Set the locked bit. This will lock out any other writes! */
- setbits_le32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
+ setbits32(&mc->security_carveout1_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
}
void tsec_region_init(void)
@@ -345,8 +345,8 @@
write32(&mc->security_carveout5_bom_hi, 0);
/* Set the locked bit. This will lock out any other writes! */
- setbits_le32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
- setbits_le32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
+ setbits32(&mc->security_carveout4_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
+ setbits32(&mc->security_carveout5_cfg0, MC_SECURITY_CARVEOUT_LOCKED);
}
void vpr_region_init(void)
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c
index 55ee50b..9117654 100644
--- a/src/soc/nvidia/tegra210/clock.c
+++ b/src/soc/nvidia/tegra210/clock.c
@@ -255,13 +255,13 @@
* FIXME: this has to be cleaned up a bit more.
* Waiting on some new info from Nvidia.
*/
- clrbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
+ clrbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0 | SOR0_CLK_SEL1);
}
void sor_clock_start(void)
{
/* uses PLLP, has a non-standard bit layout. */
- setbits_le32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0);
+ setbits32(CLK_RST_REG(clk_src_sor), SOR0_CLK_SEL0);
}
static void init_pll(u32 index, u32 osc)
@@ -280,13 +280,13 @@
/* Set Lock bit if needed. */
if (pll_reg->lock_enb_val)
- setbits_le32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val);
+ setbits32(pll_reg->lock_enb_reg, pll_reg->lock_enb_val);
/* Set KCP/KVCO if needed. */
if (pll_reg->kcp_kvco_reg)
- setbits_le32(pll_reg->kcp_kvco_reg,
- pll->kcp << pll_reg->kcp_shift |
- pll->kvco << pll_reg->kvco_shift);
+ setbits32(pll_reg->kcp_kvco_reg,
+ pll->kcp << pll_reg->kcp_shift |
+ pll->kvco << pll_reg->kvco_shift);
/* Enable PLL and take it back out of BYPASS */
write32(pll_reg->base_reg, dividers | PLL_BASE_ENABLE);
@@ -300,10 +300,10 @@
static void init_pllc(u32 osc)
{
/* Clear PLLC reset */
- clrbits_le32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET);
+ clrbits32(CLK_RST_REG(pllc_misc), PLLC_MISC_RESET);
/* Clear PLLC IDDQ */
- clrbits_le32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ);
+ clrbits32(CLK_RST_REG(pllc_misc_1), PLLC_MISC_1_IDDQ);
/* Max out the AVP clock before everything else (need PLLC for that). */
init_pll(PLLC_INDEX, osc);
@@ -316,7 +316,7 @@
static void init_pllu(u32 osc)
{
/* Clear PLLU IDDQ */
- clrbits_le32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ);
+ clrbits32(CLK_RST_REG(pllu_misc), PLLU_MISC_IDDQ);
/* Wait 5 us */
udelay(5);
@@ -508,13 +508,13 @@
{
switch (clk_id) {
case 1:
- setbits_le32(&pmc->clk_out_cntrl, 1 << 2);
+ setbits32(&pmc->clk_out_cntrl, 1 << 2);
break;
case 2:
- setbits_le32(&pmc->clk_out_cntrl, 1 << 10);
+ setbits32(&pmc->clk_out_cntrl, 1 << 10);
break;
case 3:
- setbits_le32(&pmc->clk_out_cntrl, 1 << 18);
+ setbits32(&pmc->clk_out_cntrl, 1 << 18);
break;
default:
printk(BIOS_CRIT, "ERROR: Unknown output clock id %d\n",
@@ -555,7 +555,7 @@
(p << PLL_BASE_DIVP_SHIFT));
write32(CLK_RST_REG(pllm_base), base);
- setbits_le32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE);
+ setbits32(CLK_RST_REG(pllm_base), PLL_BASE_ENABLE);
/* stable_time is required, before we can start to check lock. */
udelay(stable_time);
@@ -587,8 +587,8 @@
{
u32 osc = clock_get_osc_bits();
/* clk_m = osc/2 */
- clrsetbits_le32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK,
- CLK_M_DIVISOR_BY_2);
+ clrsetbits32(CLK_RST_REG(spare_reg0), CLK_M_DIVISOR_MASK,
+ CLK_M_DIVISOR_BY_2);
/* TIMERUS needs to be adjusted for new 19.2MHz CLK_M rate */
write32((void *)TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG,
@@ -608,7 +608,7 @@
SCLK_SOURCE_PLLC_OUT1 << SCLK_RUN_SHIFT);
/* Change the oscillator drive strength (from U-Boot -- why?) */
- clrsetbits_le32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
+ clrsetbits32(CLK_RST_REG(osc_ctrl), OSC_XOFS_MASK,
OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT);
/*
@@ -616,11 +616,11 @@
* "should update same value in PMC_OSC_EDPD_OVER XOFS
* field for warmboot "
*/
- clrsetbits_le32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
- OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
+ clrsetbits32(&pmc->osc_edpd_over, PMC_OSC_EDPD_OVER_XOFS_MASK,
+ OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT);
/* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */
- clrbits_le32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK);
+ clrbits32(CLK_RST_REG(pllx_misc3), PLLX_IDDQ_MASK);
/* Set up PLLP_OUT(1|2|3|4) divisor to generate (9.6|48|102|204)MHz */
write32(CLK_RST_REG(pllp_outa),
diff --git a/src/soc/nvidia/tegra210/cpu.c b/src/soc/nvidia/tegra210/cpu.c
index 8d74bd3..4f236c0 100644
--- a/src/soc/nvidia/tegra210/cpu.c
+++ b/src/soc/nvidia/tegra210/cpu.c
@@ -58,7 +58,7 @@
*/
write32(&sb->sb_aa64_reset_low, (uintptr_t)entry_64);
- setbits_le32(&sb->sb_aa64_reset_low, 1);
+ setbits32(&sb->sb_aa64_reset_low, 1);
write32(&sb->sb_aa64_reset_high, 0);
}
diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c
index 75376d9..2984abe 100644
--- a/src/soc/nvidia/tegra210/dma.c
+++ b/src/soc/nvidia/tegra210/dma.c
@@ -94,7 +94,7 @@
* Set global enable bit, otherwise register access to channel
* DMA registers will not be possible.
*/
- setbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+ setbits32(&apb_dma->command, APB_COMMAND_GEN);
for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) {
regs = apb_dma_channels[i].regs;
@@ -134,7 +134,7 @@
return;
}
- clrbits_le32(&apb_dma->command, APB_COMMAND_GEN);
+ clrbits32(&apb_dma->command, APB_COMMAND_GEN);
}
int dma_start(struct apb_dma_channel * const channel)
@@ -142,7 +142,7 @@
struct apb_dma_channel_regs *regs = channel->regs;
/* Set ENB bit for this channel */
- setbits_le32(®s->csr, APB_CSR_ENB);
+ setbits32(®s->csr, APB_CSR_ENB);
return 0;
}
@@ -152,7 +152,7 @@
struct apb_dma_channel_regs *regs = channel->regs;
/* Clear ENB bit for this channel */
- clrbits_le32(®s->csr, APB_CSR_ENB);
+ clrbits32(®s->csr, APB_CSR_ENB);
return 0;
}
diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h
index 6d8c338..8c4530c 100644
--- a/src/soc/nvidia/tegra210/include/soc/clock.h
+++ b/src/soc/nvidia/tegra210/include/soc/clock.h
@@ -320,8 +320,8 @@
printk(BIOS_ERR, "%s clock divisor overflow!", name);
hlt();
}
- clrsetbits_le32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
- src << CLK_SOURCE_SHIFT | div);
+ clrsetbits32(reg, CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
+ src << CLK_SOURCE_SHIFT | div);
}
#define get_i2c_clk_div(src, freq) \
diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c
index e1d91fd..ce61547 100644
--- a/src/soc/nvidia/tegra210/sdram.c
+++ b/src/soc/nvidia/tegra210/sdram.c
@@ -34,7 +34,7 @@
static void writebits(uint32_t value, uint32_t *addr, uint32_t mask)
{
- clrsetbits_le32(addr, mask, (value & mask));
+ clrsetbits32(addr, mask, (value & mask));
}
static void sdram_trigger_emc_timing_update(struct tegra_emc_regs *regs)
@@ -82,15 +82,15 @@
u32 clk_source_emc = param->EmcClockSource;
/* Enable the clocks for EMC and MC */
- setbits_le32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC
- setbits_le32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC
+ setbits32(&clk_rst->clk_enb_h_set, (1 << 25)); // ENB_EMC
+ setbits32(&clk_rst->clk_enb_h_set, (1 << 0)); // ENB_MC
if ((clk_source_emc >> EMC_2X_CLK_SRC_SHIFT) != PLLM_UD)
- setbits_le32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL);
+ setbits32(&clk_rst->clk_enb_x_set, CLK_ENB_EMC_DLL);
/* Remove the EMC and MC controllers from reset */
- clrbits_le32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC
- clrbits_le32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC
+ clrbits32(&clk_rst->rst_dev_h, (1 << 25)); // SWR_EMC
+ clrbits32(&clk_rst->rst_dev_h, (1 << 0)); // SWR_MC
clk_source_emc |= (is_same_freq << 16);
@@ -818,9 +818,9 @@
(param->EmcPinGpio << EMC_PIN_GPIO_SHIFT);
write32(®s->pin, val);
- clrbits_le32(®s->pin,
- (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
- EMC_PIN_CKE_MASK));
+ clrbits32(®s->pin,
+ (EMC_PIN_RESET_MASK | EMC_PIN_DQM_MASK |
+ EMC_PIN_CKE_MASK));
/*
* Assert dummy read of PIN register to ensure above write goes
* through. Wait an additional 200us here as per NVIDIA.
@@ -829,7 +829,7 @@
udelay(param->EmcPinExtraWait + 200);
/* Deassert reset */
- setbits_le32(®s->pin, EMC_PIN_RESET_INACTIVE);
+ setbits32(®s->pin, EMC_PIN_RESET_INACTIVE);
/*
* Assert dummy read of PIN register to ensure above write goes
@@ -840,7 +840,7 @@
}
/* Enable clock enable signal */
- setbits_le32(®s->pin, EMC_PIN_CKE_NORMAL);
+ setbits32(®s->pin, EMC_PIN_CKE_NORMAL);
/* Dummy read of PIN register to ensure final write goes through */
dummy |= read32(®s->pin);
@@ -1005,7 +1005,7 @@
/* TODO(hungte) Move values here to standalone header file. */
uint32_t *ahb_arbitration_xbar_ctrl = (uint32_t *)(AHB_ARB_XBAR_CTRL);
- setbits_le32(ahb_arbitration_xbar_ctrl,
+ setbits32(ahb_arbitration_xbar_ctrl,
param->AhbArbitrationXbarCtrlMemInitDone << 16);
}
diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c
index 5a065ba..b0142a4 100644
--- a/src/soc/nvidia/tegra210/spi.c
+++ b/src/soc/nvidia/tegra210/spi.c
@@ -188,13 +188,13 @@
return NULL;
/* software drives chip-select, set value to high */
- setbits_le32(&spi->regs->command1,
+ setbits32(&spi->regs->command1,
SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL);
/* 8-bit transfers, unpacked mode, most significant bit first */
- clrbits_le32(&spi->regs->command1,
+ clrbits32(&spi->regs->command1,
SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED);
- setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
+ setbits32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT);
return spi;
}
@@ -263,7 +263,7 @@
static void clear_fifo_status(struct tegra_spi_channel *spi)
{
- clrbits_le32(&spi->regs->fifo_status,
+ clrbits32(&spi->regs->fifo_status,
SPI_FIFO_STATUS_ERR |
SPI_FIFO_STATUS_TX_FIFO_OVF |
SPI_FIFO_STATUS_TX_FIFO_UNR |
@@ -374,7 +374,7 @@
*/
write32(&spi->regs->dma_blk, todo - 1);
- setbits_le32(&spi->regs->command1, enable_mask);
+ setbits32(&spi->regs->command1, enable_mask);
if (dir == SPI_SEND) {
unsigned int to_fifo = bytes;
@@ -390,7 +390,7 @@
static void tegra_spi_pio_start(struct tegra_spi_channel *spi)
{
- setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
+ setbits32(&spi->regs->trans_status, SPI_STATUS_RDY);
/*
* Need to stabilize other reg bit before GO bit set.
*
@@ -403,7 +403,7 @@
* enabling pio or dma.
*/
udelay(2);
- setbits_le32(&spi->regs->command1, SPI_CMD1_GO);
+ setbits32(&spi->regs->command1, SPI_CMD1_GO);
/* Need to wait a few cycles before command1 register is read */
udelay(1);
/* Make sure the write to command1 completes. */
@@ -421,7 +421,7 @@
{
u8 *p = spi->in_buf;
- clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
+ clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN);
ASSERT(rx_fifo_count(spi) == spi_byte_count(spi));
@@ -447,19 +447,19 @@
struct apb_dma_channel *dma)
{
/* APB bus width = 8-bits, address wrap for each word */
- clrbits_le32(&dma->regs->apb_seq,
+ clrbits32(&dma->regs->apb_seq,
APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT);
/* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
* no address wrapping */
- clrsetbits_le32(&dma->regs->ahb_seq,
+ clrsetbits32(&dma->regs->ahb_seq,
(AHB_BURST_MASK << AHB_BURST_SHIFT),
4 << AHB_BURST_SHIFT);
/* Set ONCE mode to transfer one "block" at a time (64KB) and enable
* flow control. */
- clrbits_le32(&dma->regs->csr,
+ clrbits32(&dma->regs->csr,
APB_CSR_REQ_SEL_MASK << APB_CSR_REQ_SEL_SHIFT);
- setbits_le32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW |
+ setbits32(&dma->regs->csr, APB_CSR_ONCE | APB_CSR_FLOW |
(spi->req_sel << APB_CSR_REQ_SEL_SHIFT));
}
@@ -496,7 +496,7 @@
write32(&spi->dma_out->regs->apb_ptr,
(uintptr_t) & spi->regs->tx_fifo);
write32(&spi->dma_out->regs->ahb_ptr, (uintptr_t)spi->out_buf);
- setbits_le32(&spi->dma_out->regs->csr, APB_CSR_DIR);
+ setbits32(&spi->dma_out->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_out);
write32(&spi->dma_out->regs->wcount, wcount);
} else {
@@ -510,7 +510,7 @@
write32(&spi->dma_in->regs->apb_ptr,
(uintptr_t)&spi->regs->rx_fifo);
write32(&spi->dma_in->regs->ahb_ptr, (uintptr_t)spi->in_buf);
- clrbits_le32(&spi->dma_in->regs->csr, APB_CSR_DIR);
+ clrbits32(&spi->dma_in->regs->csr, APB_CSR_DIR);
setup_dma_params(spi, spi->dma_in);
write32(&spi->dma_in->regs->wcount, wcount);
}
@@ -527,7 +527,7 @@
* (set bit to clear) between each transaction. Otherwise the next
* transaction does not start.
*/
- setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY);
+ setbits32(&spi->regs->trans_status, SPI_STATUS_RDY);
struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE;
@@ -539,21 +539,21 @@
*/
if (spi->dma_out) {
/* Enable secure access for the channel. */
- setbits_le32(&apb_dma->security_reg,
+ setbits32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_out->num));
- clrsetbits_le32(&spi->regs->dma_ctl,
+ clrsetbits32(&spi->regs->dma_ctl,
SPI_DMA_CTL_TX_TRIG_MASK << SPI_DMA_CTL_TX_TRIG_SHIFT,
1 << SPI_DMA_CTL_TX_TRIG_SHIFT);
- setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
+ setbits32(&spi->regs->command1, SPI_CMD1_TX_EN);
}
if (spi->dma_in) {
/* Enable secure access for the channel. */
- setbits_le32(&apb_dma->security_reg,
+ setbits32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_in->num));
- clrsetbits_le32(&spi->regs->dma_ctl,
+ clrsetbits32(&spi->regs->dma_ctl,
SPI_DMA_CTL_RX_TRIG_MASK << SPI_DMA_CTL_RX_TRIG_SHIFT,
1 << SPI_DMA_CTL_RX_TRIG_SHIFT);
- setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
+ setbits32(&spi->regs->command1, SPI_CMD1_RX_EN);
}
/*
@@ -562,7 +562,7 @@
*/
if (spi->dma_out)
dma_start(spi->dma_out);
- setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
+ setbits32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA);
if (spi->dma_in)
dma_start(spi->dma_in);
@@ -583,9 +583,9 @@
dma_busy(spi->dma_in))
;
dma_stop(spi->dma_in);
- clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN);
+ clrbits32(&spi->regs->command1, SPI_CMD1_RX_EN);
/* Disable secure access for the channel. */
- clrbits_le32(&apb_dma->security_reg,
+ clrbits32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_in->num));
dma_release(spi->dma_in);
}
@@ -596,10 +596,10 @@
while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) ||
dma_busy(spi->dma_out))
;
- clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN);
+ clrbits32(&spi->regs->command1, SPI_CMD1_TX_EN);
dma_stop(spi->dma_out);
/* Disable secure access for the channel. */
- clrbits_le32(&apb_dma->security_reg,
+ clrbits32(&apb_dma->security_reg,
SECURITY_EN_BIT(spi->dma_out->num));
dma_release(spi->dma_out);
}