commit 54f942499b72efe301e7bee7b7d9daf6a1d8c8ea
author Elyes HAOUAS <ehaouas@noos.fr> Thu Oct 25 10:57:39 2018 +0200
committer Patrick Georgi <pgeorgi@google.com> Mon Nov 05 08:57:57 2018 +0000
tree d5c48eeceaf59ac082c4132a6def95503446d8f7
parent 2a1c4302d1e6a6d34084989a0ef7e57e6f5a29a4

sb/intel/lynxpoint: Remove irrelevant conditional statement

After a {break,return}, "else" is generally not needed.

Change-Id: I6145424ef8ffe6854c18c1d885f579d37853a70c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29267
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/lynxpoint/me_9.x.c

diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c
index 6168498..574a830 100644
--- a/src/southbridge/intel/lynxpoint/me_9.x.c
+++ b/src/southbridge/intel/lynxpoint/me_9.x.c
@@ -650,10 +650,9 @@
 	if (mei_sendrecv_icc(&icc, &clk, sizeof(clk), NULL, 0) < 0) {
 		printk(BIOS_ERR, "ME: ICC SET CLOCK ENABLES message failed\n");
 		return -1;
-	} else {
-		printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
 	}
 
+	printk(BIOS_INFO, "ME: ICC SET CLOCK ENABLES 0x%08x\n", mask);
 	return 0;
 }
 

src/southbridge/intel/lynxpoint/usb_xhci.c

diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c
index 28e6521..41d99f6 100644
--- a/src/southbridge/intel/lynxpoint/usb_xhci.c
+++ b/src/southbridge/intel/lynxpoint/usb_xhci.c
@@ -40,20 +40,19 @@
 	if (pch_is_lp()) {
 		/* LynxPoint-LP has 4 SS ports */
 		return 4;
-	} else {
-		/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
-		u8 *mem_base = usb_xhci_mem_base(dev);
-		u32 fus = read32(mem_base + XHCI_USB3FUS);
-		fus >>= XHCI_USB3FUS_SS_SHIFT;
-		fus &= XHCI_USB3FUS_SS_MASK;
-		switch (fus) {
-		case 3: return 0;
-		case 2: return 2;
-		case 1: return 4;
-		case 0: default: return 6;
-		}
 	}
-	return 0;
+		/* LynxPoint-H can have 0, 2, 4, or 6 SS ports */
+	u8 *mem_base = usb_xhci_mem_base(dev);
+	u32 fus = read32(mem_base + XHCI_USB3FUS);
+	fus >>= XHCI_USB3FUS_SS_SHIFT;
+	fus &= XHCI_USB3FUS_SS_MASK;
+	switch (fus) {
+	case 3: return 0;
+	case 2: return 2;
+	case 1: return 4;
+	case 0:
+	default: return 6;
+	}
 }
 
 static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)