sb/intel/lynxpoint: Set PCIe L1 substates capabilities register
Copied from soc/intel/broadwell.
Test: build/boot google/beltino variants, verify L1 PM substates
listed under PCIe device capabilities
Change-Id: Ib2ae3d9539de9f7e22975f00450d9d60d1fd938a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46134
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c
index 077dcd6..2da14ed 100644
--- a/src/southbridge/intel/lynxpoint/pcie.c
+++ b/src/southbridge/intel/lynxpoint/pcie.c
@@ -676,6 +676,12 @@
else
pci_update_config32(dev, 0x100, ~0xfffff, (1 << 29));
+ /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */
+ if (CONFIG(PCIEXP_L1_SUB_STATE))
+ pci_update_config32(dev, 0x200, ~0xfffff, 0x001e);
+ else
+ pci_update_config32(dev, 0x200, ~0xfffff, 0);
+
if (is_lp)
pci_or_config32(dev, 0x100, 1 << 29);