diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c
index fccb97f..babb994 100644
--- a/src/northbridge/intel/gm45/early_reset.c
+++ b/src/northbridge/intel/gm45/early_reset.c
@@ -21,6 +21,7 @@
 
 #include <types.h>
 #include <arch/io.h>
+#include <halt.h>
 #include "gm45.h"
 
 void gm45_early_reset(void/*const timings_t *const timings*/)
@@ -69,5 +70,5 @@
 	/* Perform system reset through CF9 interface. */
 	outb(0x02, 0xcf9); /* Set system reset bit. */
 	outb(0x06, 0xcf9); /* Set cpu reset bit, too. */
-	while (1) asm("hlt");
+	halt();
 }
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index 9c694c7..5394002 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -26,6 +26,7 @@
 #include <cpu/x86/lapic.h>
 #include <cpu/intel/speedstep.h>
 #include <console/console.h>
+#include <halt.h>
 #include <spd.h>
 #include <types.h>
 #include <string.h>
@@ -1522,7 +1523,7 @@
 	printk(BIOS_INFO, "%s", msg);
 	i5000_dump_error_registers();
 	outb(0x06, 0xcf9);
-	for(;;) asm volatile("hlt");
+	halt();
 }
 
 static void i5000_pam_setup(void)
@@ -1624,7 +1625,7 @@
 		pci_write_config8(PCI_ADDR(0, 16, 1, 0), 0x56, ddrfrq);
 		/* FSB:FBD mapping changed, needs hard reset */
 		outb(0x06, 0xcf9);
-		for(;;) asm volatile("hlt");
+		halt();
 	}
 	return 0;
 }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index f639aef..aaa17e5 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -23,6 +23,7 @@
 #include <arch/io.h>
 #include <device/pci_def.h>
 #include <cbmem.h>
+#include <halt.h>
 #include <string.h>
 #include "i945.h"
 
@@ -512,7 +513,7 @@
 			reg32 |= (3 << 0);
 			DMIBAR32(0x224) = reg32;
 			outb(0x06, 0xcf9);
-			for (;;) asm("hlt");	/* wait for reset */
+			halt(); /* wait for reset */
 		}
 	}
 }
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index e823bab..e9b6e3f 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -24,6 +24,7 @@
 #include <spd.h>
 #include <string.h>
 #include <arch/io.h>
+#include <halt.h>
 #include <lib.h>
 #include "raminit.h"
 #include "i945.h"
@@ -281,7 +282,7 @@
 			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
-			for (;;) asm("hlt"); /* Wait for reset! */
+			halt(); /* Wait for reset! */
 		}
 	}
 
@@ -311,7 +312,7 @@
 		printk(BIOS_DEBUG, "Reset required.\n");
 		outb(0x00, 0xcf9);
 		outb(0x0e, 0xcf9);
-		for (;;) asm("hlt"); /* Wait for reset! */
+		halt(); /* Wait for reset! */
 	}
 }
 
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 74ddb4b..fb82484 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -28,7 +28,6 @@
 #include <stdlib.h>
 #include <console/console.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cpu/x86/msr.h>
 #include <cbmem.h>
@@ -38,6 +37,7 @@
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
 #include <arch/cpu.h>
+#include <halt.h>
 #include <spd.h>
 #include "raminit.h"
 #include <timestamp.h>
@@ -3805,9 +3805,7 @@
 		write_mchbar8(0x2ca8, 0);
 		outb(0x6, 0xcf9);
 #if REAL
-		while (1) {
-			asm volatile ("hlt");
-		}
+		halt();
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4041,9 +4039,7 @@
 			       "Interrupted RAM init, reset required.\n");
 			outb(0x6, 0xcf9);
 #if REAL
-			while (1) {
-				asm volatile ("hlt");
-			}
+			halt();
 #endif
 		}
 	}
@@ -4407,9 +4403,7 @@
 		write_mchbar8(0x2ca8, read_mchbar8(0x2ca8) + 4);
 		write_mchbar32(0x1af0, read_mchbar32(0x1af0) | 0x10);
 #if REAL
-		while (1) {
-			asm volatile ("hlt");
-		}
+		halt();
 #else
 		printf("CP5\n");
 		exit(0);
@@ -4510,9 +4504,7 @@
 			outb(0xe, 0xcf9);
 
 #if REAL
-			while (1) {
-				asm volatile ("hlt");
-			}
+			halt();
 #else
 			printf("CP5\n");
 			exit(0);
@@ -4990,7 +4982,7 @@
 
 		/* Failed S3 resume, reset to come up cleanly */
 		outb(0xe, 0xcf9);
-		hlt();
+		halt();
 	}
 #endif
 }
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index d2ae4b0..f6c92db 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -21,7 +21,6 @@
 #include <console/usb.h>
 #include <bootmode.h>
 #include <string.h>
-#include <arch/hlt.h>
 #include <arch/io.h>
 #include <cbmem.h>
 #include <arch/cbfs.h>
@@ -29,6 +28,7 @@
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
 #include <device/pci_def.h>
+#include <halt.h>
 #include "raminit.h"
 #include "pei_data.h"
 #include "sandybridge.h"
@@ -239,7 +239,7 @@
 	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
 		printk(BIOS_DEBUG, "Giving up in sdram_initialize: No MRC data\n");
 		outb(0x6, 0xcf9);
-		hlt();
+		halt();
 	}
 
 	/* Pass console handler in pei_data */