tree 39525836cb27c53d19fcc868f166eb40ed742051
parent 466edb51b4b0c19486f14f43bee8d6834c52abc9
author Raul E Rangel <rrangel@chromium.org> 1612571352 -0700
committer Felix Held <felix-coreboot@felixheld.de> 1612983682 +0000

soc/amd/cezanne: Enable SOC_AMD_COMMON_BLOCK_SPI

Required so we pass SPI information down to depthcharge.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ce819b537333c28d394c925331e3dbf260b7732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>