soc/intel/cmn/block/cse: Create CBMEM entries for payload to fill with CSE info
Currently, the payload cannot create new CBMEM entries as there is
no such infrastructure available. The Intel CSE driver in the payload
needs below CBMEM entries -
1. CBMEM_ID_CSE_INFO to -
a. Avoid reading ISH firmware version on consecutive boots.
b. Track state of PSR data during CSE downgrade operation.
2. CBMEM_ID_CSE_BP_INFO to avoid reading CSE boot partition
information on consecutive boots.
The idea here is to create required CBMEM entries in coreboot so
that later they can be consumed by the payload.
BUG=b:305898363
TEST=Store CSE version info in CBMEM area in depthcharge on Screebo
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I9561884f7b9f24d9533d2c433b4f6d062c9b1585
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83103
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/common/block/include/intelblocks/cse_layout.h b/src/soc/intel/common/block/include/intelblocks/cse_layout.h
index 4c88cc5..f5ff632 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse_layout.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse_layout.h
@@ -1,6 +1,9 @@
/* BPDT version 1.7 support */
/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef SOC_INTEL_COMMON_CSE_LAYOUT_H
+#define SOC_INTEL_COMMON_CSE_LAYOUT_H
+
#include <sys/types.h>
enum bpdt_entry_type {
@@ -103,3 +106,11 @@
uint16_t hotfix;
} binary_version;
} __packed;
+
+#define BPDT_HEADER_SZ sizeof(struct bpdt_header)
+#define BPDT_ENTRY_SZ sizeof(struct bpdt_entry)
+#define SUBPART_HEADER_SZ sizeof(struct subpart_hdr)
+#define SUBPART_ENTRY_SZ sizeof(struct subpart_entry)
+#define SUBPART_MANIFEST_HDR_SZ sizeof(struct subpart_entry_manifest_header)
+
+#endif // SOC_INTEL_COMMON_CSE_LAYOUT_H