soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
This patch ensures to update the FSP-M UPDs related to PCIe RP mask
properly as per the SoC type.
For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse
PCIe RPs are from PCH die in case of MTL-S.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Change-Id: Ice81553274682476bb4c927061b1196dc142836d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c
index 0173060..bdc4f7a 100644
--- a/src/soc/intel/meteorlake/romstage/fsp_params.c
+++ b/src/soc/intel/meteorlake/romstage/fsp_params.c
@@ -73,9 +73,18 @@
}
/* PCIE ports */
- m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table());
- pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,
- get_max_pcie_port());
+ if (CONFIG(SOC_INTEL_METEORLAKE_U_P)) {
+ m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(get_pcie_rp_table());
+ m_cfg->PchPcieRpEnableMask = 0; /* Don't care about PCH PCIE RP Mask */
+ pcie_rp_init(m_cfg, m_cfg->PcieRpEnableMask, config->pcie_rp,
+ get_max_pcie_port());
+ } else {
+ /*
+ * FIXME: Implement PCIe RP mask for `PchPcieRpEnableMask` and
+ * perform pcie_rp_init().
+ */
+ m_cfg->PcieRpEnableMask = 0; /* Don't care about SOC/IOE PCIE RP Mask */
+ }
}
static void fill_fspm_igd_params(FSP_M_CONFIG *m_cfg,