cpuid: Add helper function for cpuid(1) functions
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 04ef3d5..1bc3110 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -24,7 +24,7 @@
static void report_cpu_info(void)
{
struct cpuid_result cpuidr;
- u32 i, index;
+ u32 i, index, cpu_id, cpu_feature_flag;
char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
msr_t microcode_ver;
@@ -51,12 +51,15 @@
microcode_ver.lo = 0;
microcode_ver.hi = 0;
wrmsr(IA32_BIOS_SIGN_ID, microcode_ver);
- cpuidr = cpuid(1);
+ cpu_id = cpu_get_cpuid();
microcode_ver = rdmsr(IA32_BIOS_SIGN_ID);
- printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
- aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
- txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
- vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpu_id,
+ microcode_ver.hi, cpu_name);
+
+ cpu_feature_flag = cpu_get_feature_flags_ecx();
+ aes = (cpu_feature_flag & CPUID_AES) ? 1 : 0;
+ txt = (cpu_feature_flag & CPUID_SMX) ? 1 : 0;
+ vt = (cpu_feature_flag & CPUID_VMX) ? 1 : 0;
printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
mode[aes], mode[txt], mode[vt]);
}
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 46d5de8..5f7fd0a 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -19,6 +19,7 @@
#include <commonlib/region.h>
#include <bootmode.h>
#include <string.h>
+#include <arch/cpu.h>
#include <arch/io.h>
#include <cbmem.h>
#include <halt.h>
@@ -287,7 +288,6 @@
spd_raw_data spds[4];
struct region_device rdev;
ramctr_timing *ctrl_cached;
- struct cpuid_result cpures;
int err;
u32 cpu;
@@ -369,8 +369,7 @@
ctrl.tCK = min_tck;
/* Get architecture */
- cpures = cpuid(1);
- cpu = cpures.eax;
+ cpu = cpu_get_cpuid();
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Get DDR3 SPD data */
@@ -391,8 +390,7 @@
ctrl.tCK = min_tck;
/* Get architecture */
- cpures = cpuid(1);
- cpu = cpures.eax;
+ cpu = cpu_get_cpuid();
ctrl.sandybridge = IS_SANDY_CPU(cpu);
/* Reset DDR3 frequency */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 071f360..4ce059a 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -17,6 +17,7 @@
#include <console/console.h>
#include <string.h>
+#include <arch/cpu.h>
#include <arch/io.h>
#include <northbridge/intel/sandybridge/chip.h>
#include <device/pci_def.h>
@@ -190,14 +191,12 @@
static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
{
- struct cpuid_result cpures;
u32 addr, cpu, stretch;
stretch = ctrl->ref_card_offset[channel];
/* ODT stretch: Delay ODT signal by stretch value.
* Useful for multi DIMM setups on the same channel. */
- cpures = cpuid(1);
- cpu = cpures.eax;
+ cpu = cpu_get_cpuid();
if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
if (stretch == 2)
stretch = 3;
@@ -3020,11 +3019,9 @@
void set_4f8c(void)
{
- struct cpuid_result cpures;
u32 cpu;
- cpures = cpuid(1);
- cpu = (cpures.eax);
+ cpu = cpu_get_cpuid();
if (IS_SANDY_CPU(cpu) && (IS_SANDY_CPU_D0(cpu) || IS_SANDY_CPU_D1(cpu))) {
MCHBAR32(0x4f8c) = 0x141D1519;
} else {