soc/amd/common: Add coreboot post codes to STB
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
diff --git a/src/soc/amd/common/block/include/amdblocks/stb.h b/src/soc/amd/common/block/include/amdblocks/stb.h
index 51b0194..c8851f8 100644
--- a/src/soc/amd/common/block/include/amdblocks/stb.h
+++ b/src/soc/amd/common/block/include/amdblocks/stb.h
@@ -7,6 +7,7 @@
#define AMD_STB_PMI_0 0x30600
+#define AMD_STB_COREBOOT_POST_PREFIX 0xBA000000
#define AMD_STB_COREBOOT_MARKER 0xBAADF00D
struct stb_entry_struct {
diff --git a/src/soc/amd/common/block/stb/Kconfig b/src/soc/amd/common/block/stb/Kconfig
index 8935e92..fe2b5b7 100644
--- a/src/soc/amd/common/block/stb/Kconfig
+++ b/src/soc/amd/common/block/stb/Kconfig
@@ -14,4 +14,10 @@
points through the boot process. Note that this will prevent the
entries from being stored if the Spill-to-DRAM feature is enabled.
+config ADD_POSTCODES_TO_STB
+ bool "Add coreboot postcodes to STB"
+ default y
+ help
+ Add coreboot's postcodes to the smart trace buffer
+
endif
diff --git a/src/soc/amd/common/block/stb/stb.c b/src/soc/amd/common/block/stb/stb.c
index 074a4ed..0cea5c3 100644
--- a/src/soc/amd/common/block/stb/stb.c
+++ b/src/soc/amd/common/block/stb/stb.c
@@ -18,6 +18,12 @@
return smn_read32(STB_CFG_SMN_ADDR + reg);
}
+void soc_post_code(uint8_t value)
+{
+ if (CONFIG(ADD_POSTCODES_TO_STB))
+ stb_write32(AMD_STB_PMI_0, AMD_STB_COREBOOT_POST_PREFIX | value);
+}
+
void write_stb_to_console(void)
{
int i;