soc/intel/{adl, common}: Add routines into CSE IA-common code
This patch adds routines to keep CSE and other HECI devices into the
lower power device state (AKA D0I3).
- cse_set_to_d0i3 => Set CSE device state to D0I3
- heci_set_to_d0i3 => Function sets D0I3 for all HECI devices
Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI
device count info from SoC layer to common CSE block.
As per PCH EDS, the HECI device count for various SoCs are:
ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4)
APL => 1 (CSE)
SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3)
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c
index 880e1e0..b31395d 100644
--- a/src/soc/intel/alderlake/finalize.c
+++ b/src/soc/intel/alderlake/finalize.c
@@ -80,23 +80,6 @@
sa_lock_pam();
}
-static void heci_finalize(void)
-{
- unsigned int cse_dev[] = {
- PCH_DEVFN_CSE,
- PCH_DEVFN_CSE_2,
- PCH_DEVFN_CSE_3,
- PCH_DEVFN_CSE_4
- };
-
- for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
- if (!is_cse_devfn_visible(cse_dev[i]))
- continue;
-
- set_cse_device_state(cse_dev[i], DEV_IDLE);
- }
-}
-
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
@@ -105,7 +88,7 @@
apm_control(APM_CNT_FINALIZE);
tbt_finalize();
sa_finalize();
- heci_finalize();
+ heci_set_to_d0i3();
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
heci1_disable();
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index cd0abf7..38e7491 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -120,6 +120,10 @@
config DISABLE_HECI1_AT_PRE_BOOT
default y
+config MAX_HECI_DEVICES
+ int
+ default 1
+
config MAX_CPUS
int
default 4
diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig
index 1a112bd6..164159c 100644
--- a/src/soc/intel/common/block/cse/Kconfig
+++ b/src/soc/intel/common/block/cse/Kconfig
@@ -1,10 +1,3 @@
-config SOC_INTEL_COMMON_BLOCK_CSE
- bool
- default n
- help
- Driver for communication with Converged Security Engine (CSE)
- over Host Embedded Controller Interface (HECI)
-
config DISABLE_HECI1_AT_PRE_BOOT
bool "Disable HECI1 at the end of boot"
depends on SOC_INTEL_COMMON_BLOCK_CSE
@@ -14,6 +7,17 @@
Mainboard users to select this config to make HECI1 `function disable`
prior to handing off to payload.
+config MAX_HECI_DEVICES
+ int
+ default 6
+
+config SOC_INTEL_COMMON_BLOCK_CSE
+ bool
+ default n
+ help
+ Driver for communication with Converged Security Engine (CSE)
+ over Host Embedded Controller Interface (HECI)
+
config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI
bool
default y if HECI_DISABLE_USING_SMM
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 32f6d4f..6dfe329 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -988,6 +988,26 @@
return true;
}
+void cse_set_to_d0i3(void)
+{
+ if (!is_cse_devfn_visible(PCH_DEVFN_CSE))
+ return;
+
+ set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);
+}
+
+/* Function to set D0I3 for all HECI devices */
+void heci_set_to_d0i3(void)
+{
+ for (int i = 0; i < CONFIG_MAX_HECI_DEVICES; i++) {
+ pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEV_SLOT_CSE), PCI_FUNC(i));
+ if (!is_cse_devfn_visible(dev))
+ continue;
+
+ set_cse_device_state(dev, DEV_IDLE);
+ }
+}
+
#if ENV_RAMSTAGE
/*
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 15b7313..c2efab1 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -489,6 +489,12 @@
/* Function to make cse disable using PMC IPC */
bool cse_disable_mei_devices(void);
+/* Set CSE device state to D0I3 */
+void cse_set_to_d0i3(void);
+
+/* Function sets D0I3 for all HECI devices */
+void heci_set_to_d0i3(void);
+
/*
* SoC override API to make heci1 disable using PCR.
*
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 31e733c..5addfb2 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -87,6 +87,10 @@
select UDELAY_TSC
select UDK_2015_BINDING
+config MAX_HECI_DEVICES
+ int
+ default 5
+
config MAX_CPUS
int
default 16 if MAINBOARD_SUPPORTS_COFFEELAKE_CPU
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index 0f025ac..32c2380 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -75,6 +75,10 @@
int
default 2
+config MAX_HECI_DEVICES
+ int
+ default 5
+
# For 2S config, the number of cpus could be as high as
# 2 threads * 20 cores * 2 sockets
config MAX_CPUS