src/soc: Fix various typos
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
index 1798de5..02aeefe 100644
--- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S
+++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S
@@ -389,7 +389,7 @@
* Maximizing RO cacheability while locking in the CAR to a
* single way since that particular way won't be victim candidate
* for evictions.
- * This has been done after programing LLC_WAY_MASK_1 MSR
+ * This has been done after programming LLC_WAY_MASK_1 MSR
* with desired LLC way as mentioned below.
*
* Hence create Code and Data Size as per request
diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index 0ff999e..4991db6 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -31,7 +31,7 @@
/* Wait up to 15 sec for HECI to get ready */
#define HECI_DELAY_READY (15 * 1000)
-/* Wait up to 100 usec between circullar buffer polls */
+/* Wait up to 100 usec between circular buffer polls */
#define HECI_DELAY 100
/* Wait up to 5 sec for CSE to chew something we sent */
#define HECI_SEND_TIMEOUT (5 * 1000)
@@ -126,7 +126,7 @@
static uint32_t read_bar(uint32_t offset)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- /* Reach PCI config space to get BAR incase CAR global not available */
+ /* Reach PCI config space to get BAR in case CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return read32((void *)(cse->sec_bar + offset));
@@ -135,7 +135,7 @@
static void write_bar(uint32_t offset, uint32_t val)
{
struct cse_device *cse = car_get_var_ptr(&g_cse);
- /* Reach PCI config space to get BAR incase CAR global not available */
+ /* Reach PCI config space to get BAR in case CAR global not available */
if (!cse->sec_bar)
cse->sec_bar = get_cse_bar();
return write32((void *)(cse->sec_bar + offset), val);
@@ -341,7 +341,7 @@
/*
* Fragment the message into smaller messages not exceeding
- * useful circullar buffer length. Mark last message complete.
+ * useful circular buffer length. Mark last message complete.
*/
do {
hdr = MIN(max_length, remaining)
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index 5b2527c..dcf8200 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -24,7 +24,7 @@
__attribute__((weak)) void graphics_soc_init(struct device *dev)
{
/*
- * User needs to implement SoC override incase wishes
+ * User needs to implement SoC override in case wishes
* to perform certain specific graphics initialization
* along with pci_dev_init(dev)
*/
diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h
index 73a9c9c..927da3c 100644
--- a/src/soc/intel/common/block/include/intelblocks/acpi.h
+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h
@@ -44,7 +44,7 @@
struct acpi_rsdp *rsdp);
/*
- * Craetes acpi gnvs and adds it to the DSDT table.
+ * Creates acpi gnvs and adds it to the DSDT table.
* GNVS creation is chipset specific and is done in soc specific acpi.c file.
*/
void southbridge_inject_dsdt(device_t device);
@@ -84,7 +84,7 @@
/*
* soc specific power states generation. We need this to be defined by soc
* as the state generations varies in chipsets e.g. APL generates T and P
- * states while SKL generates * P state only depening on a devicetree config
+ * states while SKL generates * P state only depending on a devicetree config
*/
void soc_power_states_generation(int core_id, int cores_per_package);
diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 554c75d..7269bef 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -69,14 +69,14 @@
void lpc_open_mmio_window(uintptr_t base, size_t size);
/* Returns true if given window is decoded to LPC via a fixed range. */
bool lpc_fits_fixed_mmio_window(uintptr_t base, size_t size);
-/* Init SoC Spcific LPC features. Common definition will be weak and
+/* Init SoC Specific LPC features. Common definition will be weak and
each soc will need to define the init. */
void lpc_soc_init(struct device *dev);
/* Fill up LPC IO resource structure inside SoC directory */
void pch_lpc_soc_fill_io_resources(struct device *dev);
/* Init LPC GPIO pads */
void lpc_configure_pads(void);
-/* Get SoC speicific MMIO ranges */
+/* Get SoC specific MMIO ranges */
const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void);
/* Set LPC BIOS Control BILD bit. */
void lpc_set_bios_interface_lock_down(void);
@@ -97,7 +97,7 @@
void lpc_io_setup_comm_a_b(void);
/* Enable PCH LPC by setting up generic decode range registers. */
void pch_enable_lpc(void);
-/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */
+/* Retrieve and setup SoC specific PCH LPC interrupt routing. */
void soc_pch_pirq_init(const struct device *dev);
/* Get SoC's generic IO decoder range register settings. */
void soc_get_gen_io_dec_range(const struct device *dev,
diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h
index 3827cf5..d631f01 100644
--- a/src/soc/intel/common/block/include/intelblocks/pmclib.h
+++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h
@@ -37,7 +37,7 @@
/*
* This function is specific to soc and is defined as weak in common
* pmclib file. SOC code can implement it for any special condition
- * specific to the soc e.g. in SKL in handles deep S3 scenerio.
+ * specific to the soc e.g. in SKL in handles deep S3 scenario.
* Return ACPI_SX values to indicate the previous sleep state.
*/
int soc_prev_sleep_state(const struct chipset_power_state *ps,
@@ -206,7 +206,7 @@
void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2);
/*
- * Reads soc specific power management crtitical registers, fills
+ * Reads soc specific power management critical registers, fills
* chipset_power_state structure variable and prints.
*/
void soc_fill_power_state(struct chipset_power_state *ps);
diff --git a/src/soc/intel/common/block/include/intelblocks/systemagent.h b/src/soc/intel/common/block/include/intelblocks/systemagent.h
index 64b2c36..a731b9c 100644
--- a/src/soc/intel/common/block/include/intelblocks/systemagent.h
+++ b/src/soc/intel/common/block/include/intelblocks/systemagent.h
@@ -52,10 +52,10 @@
const char *description;
};
-/* API to set Fixed MMIO addresss into PCI configuration space */
+/* API to set Fixed MMIO address into PCI configuration space */
void sa_set_pci_bar(const struct sa_mmio_descriptor *fixed_set_resources,
size_t count);
-/* API to set Fixed MMIO addresss into MCH base address */
+/* API to set Fixed MMIO address into MCH base address */
void sa_set_mch_bar(const struct sa_mmio_descriptor *fixed_set_resources,
size_t count);
/*
@@ -69,7 +69,7 @@
* SoC to provide BIOS_RESET_CPL register offset through soc/systemagent.h
*/
void enable_bios_reset_cpl(void);
-/* API to enable PAM regisers */
+/* API to enable PAM registers */
void enable_pam_region(void);
/* API to enable Power Aware Interrupt Routing through MCHBAR */
void enable_power_aware_intr(void);
diff --git a/src/soc/intel/common/block/pcr/pcr.c b/src/soc/intel/common/block/pcr/pcr.c
index 4264cdf..e106c41 100644
--- a/src/soc/intel/common/block/pcr/pcr.c
+++ b/src/soc/intel/common/block/pcr/pcr.c
@@ -59,7 +59,7 @@
uint32_t pcr_read32(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
assert(IS_ALIGNED(offset, sizeof(uint32_t)));
return read32(__pcr_reg_address(pid, offset));
@@ -67,7 +67,7 @@
uint16_t pcr_read16(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint16_t));
return read16(__pcr_reg_address(pid, offset));
@@ -75,7 +75,7 @@
uint8_t pcr_read8(uint8_t pid, uint16_t offset)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint8_t));
return read8(__pcr_reg_address(pid, offset));
@@ -94,7 +94,7 @@
void pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
assert(IS_ALIGNED(offset, sizeof(indata)));
write32(__pcr_reg_address(pid, offset), indata);
@@ -104,7 +104,7 @@
void pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint16_t));
write16(__pcr_reg_address(pid, offset), indata);
@@ -114,7 +114,7 @@
void pcr_write8(uint8_t pid, uint16_t offset, uint8_t indata)
{
- /* Ensure the PCR offset is corretcly aligned. */
+ /* Ensure the PCR offset is correctly aligned. */
check_pcr_offset_align(offset, sizeof(uint8_t));
write8(__pcr_reg_address(pid, offset), indata);
diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index dea7e1b..cf87d05 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -360,7 +360,7 @@
/*
* Returns prev_sleep_state and also prints all power management registers.
- * Calls soc_prev_sleep_state which may be impelmented by SOC.
+ * Calls soc_prev_sleep_state which may be implemented by SOC.
*/
static int pmc_prev_sleep_state(const struct chipset_power_state *ps)
{
diff --git a/src/soc/intel/common/block/sgx/Kconfig b/src/soc/intel/common/block/sgx/Kconfig
index 7889582..0852bfb 100644
--- a/src/soc/intel/common/block/sgx/Kconfig
+++ b/src/soc/intel/common/block/sgx/Kconfig
@@ -3,5 +3,5 @@
default n
help
Software Guard eXtension(SGX) Feature. Intel SGX is a set of new CPU
- instructions that can be used by applications to set aside privat
+ instructions that can be used by applications to set aside private
regions of code and data.
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index 86789fa..d3be15c 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -193,11 +193,11 @@
msr_t msr;
msr = rdmsr(PRMRR_PHYS_MASK_MSR);
if (msr.lo & PRMRR_PHYS_MASK_VALID) {
- printk(BIOS_INFO, "SGX: MCHECK aprroved SGX PRMRR\n");
+ printk(BIOS_INFO, "SGX: MCHECK approved SGX PRMRR\n");
return 1;
}
- printk(BIOS_INFO, "SGX: MCHECK did not aprrove SGX PRMRR\n");
+ printk(BIOS_INFO, "SGX: MCHECK did not approve SGX PRMRR\n");
return 0;
}
@@ -226,7 +226,7 @@
/* Lock the SGX feature */
lock_sgx();
- /* Activate the SGX feature, if PRMRR config was aprroved by MCHECK */
+ /* Activate the SGX feature, if PRMRR config was approved by MCHECK */
if (is_prmrr_approved())
activate_sgx();
}
diff --git a/src/soc/intel/common/block/systemagent/systemagent_def.h b/src/soc/intel/common/block/systemagent/systemagent_def.h
index e028692..b89a10d 100644
--- a/src/soc/intel/common/block/systemagent/systemagent_def.h
+++ b/src/soc/intel/common/block/systemagent/systemagent_def.h
@@ -19,13 +19,13 @@
/* Device 0:0.0 PCI configuration space */
-/* GMCH Graphics Comntrol Register */
+/* GMCH Graphics Control Register */
#define GGC 0x50
#define G_GMS_OFFSET 0x8
#define G_GMS_MASK 0xff00
#define G_GGMS_OFFSET 0x6
#define G_GGMS_MASK 0xc0
-/* DPR register incase CONFIG_SA_ENABLE_DPR is selected by SoC */
+/* DPR register in case CONFIG_SA_ENABLE_DPR is selected by SoC */
#define DPR 0x5c
#define DPR_EPM (1 << 2)
#define DPR_PRS (1 << 1)
@@ -48,7 +48,7 @@
#define MCH_PAIR 0x5418
/*
- * IMR register incase CONFIG_SA_ENABLE_IMR is selected by SoC.
+ * IMR register in case CONFIG_SA_ENABLE_IMR is selected by SoC.
*
* IMR registers are found under MCHBAR.
*/
diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c
index 91badc7..9f26ef1 100644
--- a/src/soc/intel/common/block/uart/uart.c
+++ b/src/soc/intel/common/block/uart/uart.c
@@ -106,7 +106,7 @@
static bool uart_controller_needs_init(struct device *dev)
{
/*
- * If coreboot has CONSOLE_SERIAL enabled, the skip re-initalizing
+ * If coreboot has CONSOLE_SERIAL enabled, the skip re-initializing
* controller here.
*/
if (IS_ENABLED(CONFIG_CONSOLE_SERIAL))