- Cleanups on the romcc side including a pci interface that uses
fewer registers, and is easier to hardcode.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index d64acef..4e7b9e3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -161,7 +161,7 @@
#endif
#if 1
- // pick how to scan the bus. This is first so we can get at memory size.
+ /* pick how to scan the bus. This is first so we can get at memory size. */
printk_info("Finding PCI configuration type.\n");
pci_set_method();
post_code(0x5f);
@@ -170,13 +170,15 @@
#endif
dev_enumerate();
post_code(0x66);
- // Now do the real bus
- // we round the total ram up a lot for thing like the SISFB, which
- // shares high memory with the CPU.
+ /* Now do the real bus.
+ * We round the total ram up a lot for thing like the SISFB, which
+ * shares high memory with the CPU.
+ */
dev_configure();
post_code(0x88);
dev_enable();
+
dev_initialize();
post_code(0x89);
#endif