ARM: Generalize armv7 as arm.
There are ARM systems which are essentially heterogeneous multicores where
some cores implement a different ARM architecture version than other cores. A
specific example is the tegra124 which boots on an ARMv4 coprocessor while
most code, including most of the firmware, runs on the main ARMv7 core. To
support SOCs like this, the plan is to generalize the ARM architecture so that
all versions are available, and an SOC/CPU can then select what architecture
variant should be used for each component of the firmware; bootblock,
romstage, and ramstage.
Old-Change-Id: I22e048c3bc72bd56371e14200942e436c1e312c2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/171338
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8423a41529da0ff67fb9873be1e2beb30b09ae2d)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
ARM: Split out ARMv7 code and make it possible to have other arch versions.
We don't always want to use ARMv7 code when building for ARM, so we should
separate out the ARMv7 code so it can be excluded, and also make it possible
to include code for some other version of the architecture instead, all per
build component for cases where we need more than one architecture version
at a time.
The tegra124 bootblock will ultimately need to be ARMv4, but until we have
some ARMv4 code to switch over to we can leave it set to ARMv7.
Old-Change-Id: Ia982c91057fac9c252397b7c866224f103761cc7
Reviewed-on: https://chromium-review.googlesource.com/171400
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 799514e6060aa97acdcf081b5c48f965be134483)
Squashed two related patches for splitting ARM support into general
ARM support and ARMv7 specific pieces.
Change-Id: Ic6511507953a2223c87c55f90252c4a4e1dd6010
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6782
Tested-by: build bot (Jenkins)
diff --git a/Makefile b/Makefile
index a55ad67..49fbba5 100644
--- a/Makefile
+++ b/Makefile
@@ -117,7 +117,7 @@
include $(HAVE_DOTCONFIG)
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
-# FIXME: armv7/aarch64 won't build right now
+# FIXME: arm/aarch64 won't build right now
CFLAGS_x86_32 = -no-integrated-as -Qunused-arguments -target i386-elf -m32
CC_x86_32:=clang
@@ -130,8 +130,8 @@
#CFLAGS_x86_32 += -mno-sse
#endif
-CFLAGS_armv7 = -no-integrated-as -Qunused-arguments -target armv7-eabi -ccc-gcc-name $(CC_armv7)
-CC_armv7:=clang
+CFLAGS_arm = -no-integrated-as -Qunused-arguments -target arm-eabi -ccc-gcc-name $(CC_arm)
+CC_arm:=clang
CFLAGS_aarch64 = -no-integrated-as -Qunused-arguments -target aarch64-eabi -ccc-gcc-name $(CC_aarch64)
CC_aarch64:=clang
diff --git a/Makefile.inc b/Makefile.inc
index ab27df0..00e1a6c 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -68,7 +68,7 @@
subdirs-y := src/lib src/console src/device src/ec src/southbridge src/soc
subdirs-y += src/northbridge src/superio src/drivers src/cpu src/vendorcode
subdirs-y += util/cbfstool util/sconfig util/nvramtool
-subdirs-y += src/arch/armv7 src/arch/x86
+subdirs-y += src/arch/arm src/arch/x86
subdirs-y += src/mainboard/$(MAINBOARDDIR)
subdirs-y += site-local
@@ -550,7 +550,7 @@
bootsplash.jpg-file := $(call strip_quotes,$(CONFIG_BOOTSPLASH_FILE))
bootsplash.jpg-type := bootsplash
-ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
ROMSTAGE_ELF := romstage.elf
endif
ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y)
diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in
index e3e064e..2a5048c 100644
--- a/payloads/libpayload/Config.in
+++ b/payloads/libpayload/Config.in
@@ -67,10 +67,10 @@
prompt "Target Architecture"
default ARCH_X86
-config ARCH_ARMV7
- bool "ARMv7"
+config ARCH_ARM
+ bool "ARM"
help
- Support the x86 architecture
+ Support the ARM architecture
config ARCH_X86
bool "x86"
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index 6416519..d84b63b 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -91,14 +91,14 @@
include $(HAVE_DOTCONFIG)
-ARCHDIR-$(CONFIG_LP_ARCH_ARMV7) := armv7
+ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
ARCH-y := $(ARCHDIR-y)
# If architecture folder name is different from GCC binutils architecture name,
# override here.
-ARCH-$(CONFIG_LP_ARCH_ARMV7) := armv7
+ARCH-$(CONFIG_LP_ARCH_ARM) := arm
ARCH-$(CONFIG_LP_ARCH_X86) := i386
CC := $(CC_$(ARCH-y))
diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc
index 5eeb907..d3b8787 100644
--- a/payloads/libpayload/Makefile.inc
+++ b/payloads/libpayload/Makefile.inc
@@ -31,7 +31,7 @@
export KERNELVERSION := 0.2.0
-ARCHDIR-$(CONFIG_LP_ARCH_ARMV7) := armv7
+ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
DESTDIR ?= install
diff --git a/payloads/libpayload/arch/Config.in b/payloads/libpayload/arch/Config.in
index 1049da0..541f64f 100644
--- a/payloads/libpayload/arch/Config.in
+++ b/payloads/libpayload/arch/Config.in
@@ -27,5 +27,5 @@
## SUCH DAMAGE.
##
-source "arch/armv7/Config.in"
+source "arch/arm/Config.in"
source "arch/x86/Config.in"
diff --git a/payloads/libpayload/arch/armv7/Config.in b/payloads/libpayload/arch/arm/Config.in
similarity index 98%
rename from payloads/libpayload/arch/armv7/Config.in
rename to payloads/libpayload/arch/arm/Config.in
index 79cd676..b2ee527 100644
--- a/payloads/libpayload/arch/armv7/Config.in
+++ b/payloads/libpayload/arch/arm/Config.in
@@ -27,7 +27,7 @@
## SUCH DAMAGE.
##
-if ARCH_ARMV7
+if ARCH_ARM
config ARCH_SPECIFIC_OPTIONS # dummy
def_bool y
diff --git a/payloads/libpayload/arch/armv7/Makefile.inc b/payloads/libpayload/arch/arm/Makefile.inc
similarity index 100%
rename from payloads/libpayload/arch/armv7/Makefile.inc
rename to payloads/libpayload/arch/arm/Makefile.inc
diff --git a/payloads/libpayload/arch/armv7/assembler.h b/payloads/libpayload/arch/arm/assembler.h
similarity index 100%
rename from payloads/libpayload/arch/armv7/assembler.h
rename to payloads/libpayload/arch/arm/assembler.h
diff --git a/payloads/libpayload/arch/armv7/cache.c b/payloads/libpayload/arch/arm/cache.c
similarity index 99%
rename from payloads/libpayload/arch/armv7/cache.c
rename to payloads/libpayload/arch/arm/cache.c
index 3af7cbd..3944818 100644
--- a/payloads/libpayload/arch/armv7/cache.c
+++ b/payloads/libpayload/arch/arm/cache.c
@@ -267,7 +267,6 @@
write_sctlr(sctlr);
}
-
void dcache_mmu_enable(void)
{
uint32_t sctlr;
@@ -278,7 +277,7 @@
write_sctlr(sctlr);
}
-void armv7_invalidate_caches(void)
+void arm_invalidate_caches(void)
{
uint32_t clidr;
int level;
diff --git a/payloads/libpayload/arch/armv7/coreboot.c b/payloads/libpayload/arch/arm/coreboot.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/coreboot.c
rename to payloads/libpayload/arch/arm/coreboot.c
diff --git a/payloads/libpayload/arch/armv7/dummy_media.c b/payloads/libpayload/arch/arm/dummy_media.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/dummy_media.c
rename to payloads/libpayload/arch/arm/dummy_media.c
diff --git a/payloads/libpayload/arch/armv7/exception.c b/payloads/libpayload/arch/arm/exception.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/exception.c
rename to payloads/libpayload/arch/arm/exception.c
diff --git a/payloads/libpayload/arch/armv7/exception_asm.S b/payloads/libpayload/arch/arm/exception_asm.S
similarity index 100%
rename from payloads/libpayload/arch/armv7/exception_asm.S
rename to payloads/libpayload/arch/arm/exception_asm.S
diff --git a/payloads/libpayload/arch/armv7/head.S b/payloads/libpayload/arch/arm/head.S
similarity index 100%
rename from payloads/libpayload/arch/armv7/head.S
rename to payloads/libpayload/arch/arm/head.S
diff --git a/payloads/libpayload/arch/armv7/libpayload.ldscript b/payloads/libpayload/arch/arm/libpayload.ldscript
similarity index 100%
rename from payloads/libpayload/arch/armv7/libpayload.ldscript
rename to payloads/libpayload/arch/arm/libpayload.ldscript
diff --git a/payloads/libpayload/arch/armv7/main.c b/payloads/libpayload/arch/arm/main.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/main.c
rename to payloads/libpayload/arch/arm/main.c
diff --git a/payloads/libpayload/arch/armv7/memcpy.S b/payloads/libpayload/arch/arm/memcpy.S
similarity index 100%
rename from payloads/libpayload/arch/armv7/memcpy.S
rename to payloads/libpayload/arch/arm/memcpy.S
diff --git a/payloads/libpayload/arch/armv7/memset.S b/payloads/libpayload/arch/arm/memset.S
similarity index 100%
rename from payloads/libpayload/arch/armv7/memset.S
rename to payloads/libpayload/arch/arm/memset.S
diff --git a/payloads/libpayload/arch/armv7/sysinfo.c b/payloads/libpayload/arch/arm/sysinfo.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/sysinfo.c
rename to payloads/libpayload/arch/arm/sysinfo.c
diff --git a/payloads/libpayload/arch/armv7/timer.c b/payloads/libpayload/arch/arm/timer.c
similarity index 96%
rename from payloads/libpayload/arch/armv7/timer.c
rename to payloads/libpayload/arch/arm/timer.c
index 9449c9f..3902308 100644
--- a/payloads/libpayload/arch/armv7/timer.c
+++ b/payloads/libpayload/arch/arm/timer.c
@@ -28,8 +28,8 @@
*/
/**
- * @file armv7/timer.c
- * ARMv7 specific timer routines
+ * @file arm/timer.c
+ * ARM specific timer routines
*/
#include <libpayload.h>
diff --git a/payloads/libpayload/arch/armv7/util.S b/payloads/libpayload/arch/arm/util.S
similarity index 100%
rename from payloads/libpayload/arch/armv7/util.S
rename to payloads/libpayload/arch/arm/util.S
diff --git a/payloads/libpayload/arch/armv7/virtual.c b/payloads/libpayload/arch/arm/virtual.c
similarity index 100%
rename from payloads/libpayload/arch/armv7/virtual.c
rename to payloads/libpayload/arch/arm/virtual.c
diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
index 32ec568..a555bcb 100755
--- a/payloads/libpayload/bin/lpgcc
+++ b/payloads/libpayload/bin/lpgcc
@@ -68,11 +68,11 @@
exit 1
fi
-if [ "$CONFIG_LP_ARCH_ARMV7" = "y" ]; then
- _ARCHINCDIR=$_INCDIR/armv7
- _ARCHLIBDIR=$_LIBDIR/armv7
+if [ "$CONFIG_LP_ARCH_ARM" = "y" ]; then
+ _ARCHINCDIR=$_INCDIR/arm
+ _ARCHLIBDIR=$_LIBDIR/arm
_ARCHEXTRA=""
- _ARCH=armv7
+ _ARCH=arm
fi
if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
diff --git a/payloads/libpayload/configs/config.panther b/payloads/libpayload/configs/config.panther
index ec0f11d..e3af099 100644
--- a/payloads/libpayload/configs/config.panther
+++ b/payloads/libpayload/configs/config.panther
@@ -15,7 +15,7 @@
#
# Architecture Options
#
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
# CONFIG_LP_ARCH_POWERPC is not set
CONFIG_LP_ARCH_X86=y
# CONFIG_LP_MEMMAP_RAM_ONLY is not set
diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig
index aef9fc3..f63822e 100644
--- a/payloads/libpayload/configs/defconfig
+++ b/payloads/libpayload/configs/defconfig
@@ -15,7 +15,7 @@
#
# Architecture Options
#
-# CONFIG_LP_ARCH_ARMV7 is not set
+# CONFIG_LP_ARCH_ARM is not set
CONFIG_LP_ARCH_X86=y
# CONFIG_LP_MEMMAP_RAM_ONLY is not set
# CONFIG_LP_MULTIBOOT is not set
diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm
index 55552b0..e336f6a 100644
--- a/payloads/libpayload/configs/defconfig-arm
+++ b/payloads/libpayload/configs/defconfig-arm
@@ -15,7 +15,7 @@
#
# Architecture Options
#
-CONFIG_LP_ARCH_ARMV7=y
+CONFIG_LP_ARCH_ARM=y
# CONFIG_LP_ARCH_X86 is not set
# CONFIG_LP_MEMMAP_RAM_ONLY is not set
@@ -35,6 +35,7 @@
# CONFIG_LP_SKIP_CONSOLE_INIT is not set
CONFIG_LP_CBMEM_CONSOLE=y
CONFIG_LP_SERIAL_CONSOLE=y
+# CONFIG_LP_8250_SERIAL_CONSOLE is not set
# CONFIG_LP_SERIAL_SET_SPEED is not set
# CONFIG_LP_SERIAL_ACS_FALLBACK is not set
CONFIG_LP_VIDEO_CONSOLE=y
@@ -60,10 +61,6 @@
CONFIG_LP_USB_MSC=y
CONFIG_LP_USB_GEN_HUB=y
# CONFIG_LP_USB_PCI is not set
-CONFIG_LP_USB_MEMORY=y
-CONFIG_LP_USB_OHCI_BASE_ADDRESS=0x12120000
-CONFIG_LP_USB_EHCI_BASE_ADDRESS=0x12110000
-CONFIG_LP_USB_XHCI_BASE_ADDRESS=0x12000000
# CONFIG_LP_BIG_ENDIAN is not set
CONFIG_LP_LITTLE_ENDIAN=y
# CONFIG_LP_IO_ADDRESS_SPACE is not set
diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h
similarity index 97%
rename from payloads/libpayload/include/armv7/arch/cache.h
rename to payloads/libpayload/include/arm/arch/cache.h
index 1cd9958..ffdb55a 100644
--- a/payloads/libpayload/include/armv7/arch/cache.h
+++ b/payloads/libpayload/include/arm/arch/cache.h
@@ -26,11 +26,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * cache.h: Cache maintenance API for ARMv7
+ * cache.h: Cache maintenance API for ARM
*/
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
#include <stddef.h>
#include <stdint.h>
@@ -320,8 +320,8 @@
* Generalized setup/init functions
*/
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
@@ -338,4 +338,4 @@
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
enum dcache_policy policy);
-#endif /* ARMV7_CACHE_H */
+#endif /* ARM_CACHE_H */
diff --git a/payloads/libpayload/include/armv7/arch/exception.h b/payloads/libpayload/include/arm/arch/exception.h
similarity index 100%
rename from payloads/libpayload/include/armv7/arch/exception.h
rename to payloads/libpayload/include/arm/arch/exception.h
diff --git a/payloads/libpayload/include/armv7/arch/io.h b/payloads/libpayload/include/arm/arch/io.h
similarity index 100%
rename from payloads/libpayload/include/armv7/arch/io.h
rename to payloads/libpayload/include/arm/arch/io.h
diff --git a/payloads/libpayload/include/armv7/arch/types.h b/payloads/libpayload/include/arm/arch/types.h
similarity index 100%
rename from payloads/libpayload/include/armv7/arch/types.h
rename to payloads/libpayload/include/arm/arch/types.h
diff --git a/payloads/libpayload/include/armv7/arch/virtual.h b/payloads/libpayload/include/arm/arch/virtual.h
similarity index 100%
rename from payloads/libpayload/include/armv7/arch/virtual.h
rename to payloads/libpayload/include/arm/arch/virtual.h
diff --git a/payloads/libpayload/include/cbfs_core.h b/payloads/libpayload/include/cbfs_core.h
index d908d83..6edad0e 100644
--- a/payloads/libpayload/include/cbfs_core.h
+++ b/payloads/libpayload/include/cbfs_core.h
@@ -106,7 +106,7 @@
*/
#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
#define CBFS_ARCHITECTURE_X86 0x00000001
-#define CBFS_ARCHITECTURE_ARMV7 0x00000010
+#define CBFS_ARCHITECTURE_ARM 0x00000010
/** This is a component header - every entry in the CBFS
will have this header.
diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile
index 67697e8..2029209 100644
--- a/payloads/libpayload/sample/Makefile
+++ b/payloads/libpayload/sample/Makefile
@@ -31,7 +31,7 @@
include ../.xcompile
include ../.config
-ARCH-$(CONFIG_ARCH_ARMV7) := armv7
+ARCH-$(CONFIG_ARCH_ARMV) := arm
ARCH-$(CONFIG_ARCH_POWERPC) := powerpc
ARCH-$(CONFIG_ARCH_X86) := i386
diff --git a/payloads/libpayload/util/xcompile/xcompile b/payloads/libpayload/util/xcompile/xcompile
index 09c1879..755fb18 100644
--- a/payloads/libpayload/util/xcompile/xcompile
+++ b/payloads/libpayload/util/xcompile/xcompile
@@ -106,7 +106,7 @@
CFLAGS="$CFLAGS -Wl,--build-id=none"
case "$architecture" in
- armv7 )
+ arm )
# testcc "$CC" "$CFLAGS -mcpu=cortex-a9" &&
# CFLAGS="$CFLAGS -mcpu=cortex-a9"
;;
@@ -135,13 +135,13 @@
trap clean_up EXIT
# Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7"
+SUPPORTED_ARCHITECTURE="x86 arm"
# ARM Architecture
-TARCH_armv7="armv7"
-TBFDARCH_armv7="littlearm"
-TCLIST_armv7="armv7a"
-TWIDTH_armv7="32"
+TARCH_arm="arm"
+TBFDARCH_arm="littlearm"
+TCLIST_arm="armv7a"
+TWIDTH_arm="32"
# X86 Architecture
TARCH_x86="i386"
diff --git a/payloads/tianocoreboot/libpayload.config b/payloads/tianocoreboot/libpayload.config
index c7c0720..e63fee8 100644
--- a/payloads/tianocoreboot/libpayload.config
+++ b/payloads/tianocoreboot/libpayload.config
@@ -15,7 +15,7 @@
#
# Architecture Options
#
-# CONFIG_ARCH_ARMV7 is not set
+# CONFIG_ARCH_ARM is not set
# CONFIG_ARCH_POWERPC is not set
CONFIG_ARCH_X86=y
# CONFIG_MEMMAP_RAM_ONLY is not set
diff --git a/src/Kconfig b/src/Kconfig
index 45a215593..97a4799 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -210,12 +210,12 @@
default n
select PCI
-config ARCH_ARMV7
+config ARCH_ARM
bool
default n
source src/arch/x86/Kconfig
-source src/arch/armv7/Kconfig
+source src/arch/arm/Kconfig
source src/vendorcode/Kconfig
@@ -273,7 +273,7 @@
bool
default n
select LPC_TPM if ARCH_X86
- select I2C_TPM if ARCH_ARMV7
+ select I2C_TPM if ARCH_ARM
help
Enable this option to enable TPM support in coreboot.
diff --git a/src/arch/armv7/Kconfig b/src/arch/arm/Kconfig
similarity index 71%
rename from src/arch/armv7/Kconfig
rename to src/arch/arm/Kconfig
index e272474..050cd62 100644
--- a/src/arch/armv7/Kconfig
+++ b/src/arch/arm/Kconfig
@@ -1,16 +1,18 @@
-config ARCH_BOOTBLOCK_ARMV7
+config ARCH_BOOTBLOCK_ARM
bool
default n
- select ARCH_ARMV7
+ select ARCH_ARM
-config ARCH_ROMSTAGE_ARMV7
+config ARCH_ROMSTAGE_ARM
bool
default n
-config ARCH_RAMSTAGE_ARMV7
+config ARCH_RAMSTAGE_ARM
bool
default n
+source src/arch/arm/armv7/Kconfig
+
# If a custom bootblock is necessary, this option should be "select"-ed by
# the thing that needs it, probably the CPU.
config ARM_BOOTBLOCK_CUSTOM
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/arm/Makefile.inc
similarity index 70%
rename from src/arch/armv7/Makefile.inc
rename to src/arch/arm/Makefile.inc
index 2022f20..8838edf 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/arm/Makefile.inc
@@ -23,98 +23,86 @@
###############################################################################
# Take care of subdirectories
###############################################################################
-subdirs-y += boot/
-subdirs-y += lib/
+subdirs-y += armv7/
###############################################################################
# ARM specific options
###############################################################################
-ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
-CBFSTOOL_PRE1_OPTS = -m armv7 -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
+CBFSTOOL_PRE1_OPTS = -m arm -b $(CONFIG_BOOTBLOCK_ROM_OFFSET) -H $(CONFIG_CBFS_HEADER_ROM_OFFSET) -o $(CONFIG_CBFS_ROM_OFFSET)
CBFSTOOL_PRE_OPTS = -b 0
endif
-ifeq ($(CONFIG_ARCH_ARMV7),y)
-stages_c = $(src)/arch/armv7/stages.c
-stages_o = $(obj)/arch/armv7/stages.o
+ifeq ($(CONFIG_ARCH_ARM),y)
+stages_c = $(src)/arch/arm/stages.c
+stages_o = $(obj)/arch/arm/stages.o
$(stages_o): $(stages_c) $(obj)/config.h
@printf " CC $(subst $(obj)/,,$(@))\n"
- $(CC_armv7) -I. $(CPPFLAGS_armv7) -c -o $@ $< -marm
+ $(CC_arm) -I. $(CPPFLAGS_arm) -c -o $@ $< -marm
-endif # CONFIG_ARCH_ARMV7
+endif # CONFIG_ARCH_ARM
###############################################################################
# bootblock
###############################################################################
-ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV7),y)
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARM),y)
-ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y)
-bootblock-y += bootblock.S
-bootblock-$(CONFIG_BOOTBLOCK_SIMPLE) += bootblock_simple.c
-endif
bootblock-y += id.S
$(obj)/arch/arm/id.bootblock.o: $(obj)/build.h
bootblock-y += stages.c
-bootblock-y += cache.c
bootblock-y += eabi_compat.c
bootblock-y += memset.S
bootblock-y += memcpy.S
bootblock-y += memmove.S
-bootblock-y += mmu.c
-$(objcbfs)/bootblock.debug: $(src)/arch/armv7/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h
+$(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) $(obj)/config.h
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_bootblock) -m armelf_linux_eabi -static -o $@ -L$(obj) $< -T $(src)/arch/armv7/bootblock.ld
+ $(LD_bootblock) -m armelf_linux_eabi -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld
else
- $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(src)/arch/armv7/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group
+ $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -include $(obj)/config.h -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group
endif
-endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
+endif # CONFIG_ARCH_BOOTBLOCK_ARM
###############################################################################
# romstage
###############################################################################
-ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARM),y)
romstage-y += stages.c
-romstage-y += cache.c
romstage-y += div0.c
romstage-y += eabi_compat.c
romstage-y += memset.S
romstage-y += memcpy.S
romstage-y += memmove.S
-VBOOT_STUB_DEPS += $(obj)/arch/armv7/eabi_compat.rmodules_arm.o
+VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o
-$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/armv7/romstage.ld $(obj)/ldoptions
+$(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/ldoptions
@printf " LINK $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/armv7/romstage.ld
+ $(LD_romstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld
else
- $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
+ $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group
endif
-endif # CONFIG_ARCH_ROMSTAGE_ARMV7
+endif # CONFIG_ARCH_ROMSTAGE_ARM
###############################################################################
# ramstage
###############################################################################
-ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y)
+ifeq ($(CONFIG_ARCH_RAMSTAGE_ARM),y)
ramstage-y += stages.c
-ramstage-y += exception.c
-ramstage-y += exception_asm.S
ramstage-y += div0.c
-ramstage-y += cache.c
ramstage-y += cpu.c
-ramstage-y += mmu.c
ramstage-y += eabi_compat.c
ramstage-y += boot.c
ramstage-y += tables.c
@@ -123,12 +111,12 @@
ramstage-y += memmove.S
ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c)
-$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $(src)/arch/armv7/ramstage.ld $(obj)/ldoptions
+$(objcbfs)/ramstage.debug: $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) $(src)/arch/arm/ramstage.ld $(obj)/ldoptions
@printf " CC $(subst $(obj)/,,$(@))\n"
ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y)
- $(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/armv7/ramstage.ld
+ $(LD_ramstage) -m armelf_linux_eabi -o $@ -L$(obj) $< -T $(src)/arch/arm/ramstage.ld
else
- $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/armv7/ramstage.ld
+ $(CC_ramstage) $(CFLAGS_ramstage) -nostdlib -nostartfiles -static -o $@ -L$(obj) -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group -T $(src)/arch/arm/ramstage.ld
endif
$(objgenerated)/ramstage.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage)
@@ -139,4 +127,4 @@
$(CC_ramstage) $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME_ramstage) -Wl,--end-group
endif
-endif # CONFIG_ARCH_RAMSTAGE_ARMV7
+endif # CONFIG_ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm/armv7/Kconfig b/src/arch/arm/armv7/Kconfig
new file mode 100644
index 0000000..f8e0205
--- /dev/null
+++ b/src/arch/arm/armv7/Kconfig
@@ -0,0 +1,11 @@
+config ARCH_BOOTBLOCK_ARMV7
+ def_bool n
+ select ARCH_BOOTBLOCK_ARM
+
+config ARCH_ROMSTAGE_ARMV7
+ def_bool n
+ select ARCH_ROMSTAGE_ARM
+
+config ARCH_RAMSTAGE_ARMV7
+ def_bool n
+ select ARCH_RAMSTAGE_ARM
diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc
new file mode 100644
index 0000000..bcd7d9e
--- /dev/null
+++ b/src/arch/arm/armv7/Makefile.inc
@@ -0,0 +1,71 @@
+################################################################################
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 The ChromiumOS Authors
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+###############################################################################
+
+armv7_flags = -march=armv7-a -mthumb -mthumb-interwork \
+ -I$(src)/arch/arm/include/armv7/
+
+###############################################################################
+# bootblock
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV7),y)
+
+ifneq ($(CONFIG_ARM_BOOTBLOCK_CUSTOM),y)
+bootblock-y += bootblock.S
+bootblock-$(CONFIG_BOOTBLOCK_SIMPLE) += bootblock_simple.c
+endif
+
+bootblock-y += cache.c
+bootblock-y += mmu.c
+
+CFLAGS_bootblock += $(armv7_flags)
+CPPFLAGS_bootblock += $(armv7_flags)
+
+endif # CONFIG_ARCH_BOOTBLOCK_ARMV7
+
+###############################################################################
+# romstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y)
+
+romstage-y += cache.c
+
+CFLAGS_romstage += $(armv7_flags)
+CPPFLAGS_romstage += $(armv7_flags)
+
+endif # CONFIG_ARCH_ROMSTAGE_ARMV7
+
+###############################################################################
+# ramstage
+###############################################################################
+
+ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV7),y)
+
+ramstage-y += cache.c
+ramstage-y += exception.c
+ramstage-y += exception_asm.S
+ramstage-y += mmu.c
+
+CFLAGS_ramstage += $(armv7_flags)
+CPPFLAGS_ramstage += $(armv7_flags)
+
+endif # CONFIG_ARCH_RAMSTAGE_ARMV7
diff --git a/src/arch/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
similarity index 100%
rename from src/arch/armv7/bootblock.S
rename to src/arch/arm/armv7/bootblock.S
diff --git a/src/arch/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c
similarity index 98%
rename from src/arch/armv7/bootblock_simple.c
rename to src/arch/arm/armv7/bootblock_simple.c
index bcd83b8..f447034 100644
--- a/src/arch/armv7/bootblock_simple.c
+++ b/src/arch/arm/armv7/bootblock_simple.c
@@ -39,7 +39,7 @@
sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
write_sctlr(sctlr);
- armv7_invalidate_caches();
+ arm_invalidate_caches();
/*
* Re-enable icache and branch prediction. MMU and dcache will be
diff --git a/src/arch/armv7/cache.c b/src/arch/arm/armv7/cache.c
similarity index 99%
rename from src/arch/armv7/cache.c
rename to src/arch/arm/armv7/cache.c
index 1f466ce..acd1f9a 100644
--- a/src/arch/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -276,7 +276,7 @@
write_sctlr(sctlr);
}
-void armv7_invalidate_caches(void)
+void arm_invalidate_caches(void)
{
uint32_t clidr;
int level;
diff --git a/src/arch/armv7/exception.c b/src/arch/arm/armv7/exception.c
similarity index 100%
rename from src/arch/armv7/exception.c
rename to src/arch/arm/armv7/exception.c
diff --git a/src/arch/armv7/exception_asm.S b/src/arch/arm/armv7/exception_asm.S
similarity index 100%
rename from src/arch/armv7/exception_asm.S
rename to src/arch/arm/armv7/exception_asm.S
diff --git a/src/arch/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
similarity index 100%
rename from src/arch/armv7/mmu.c
rename to src/arch/arm/armv7/mmu.c
diff --git a/src/arch/armv7/thread.c b/src/arch/arm/armv7/thread.c
similarity index 100%
rename from src/arch/armv7/thread.c
rename to src/arch/arm/armv7/thread.c
diff --git a/src/arch/armv7/boot.c b/src/arch/arm/boot.c
similarity index 100%
rename from src/arch/armv7/boot.c
rename to src/arch/arm/boot.c
diff --git a/src/arch/armv7/bootblock.ld b/src/arch/arm/bootblock.ld
similarity index 100%
rename from src/arch/armv7/bootblock.ld
rename to src/arch/arm/bootblock.ld
diff --git a/src/arch/armv7/cpu.c b/src/arch/arm/cpu.c
similarity index 100%
rename from src/arch/armv7/cpu.c
rename to src/arch/arm/cpu.c
diff --git a/src/arch/armv7/div0.c b/src/arch/arm/div0.c
similarity index 100%
rename from src/arch/armv7/div0.c
rename to src/arch/arm/div0.c
diff --git a/src/arch/armv7/eabi_compat.c b/src/arch/arm/eabi_compat.c
similarity index 100%
rename from src/arch/armv7/eabi_compat.c
rename to src/arch/arm/eabi_compat.c
diff --git a/src/arch/armv7/id.S b/src/arch/arm/id.S
similarity index 100%
rename from src/arch/armv7/id.S
rename to src/arch/arm/id.S
diff --git a/src/arch/armv7/include/arch/boot/boot.h b/src/arch/arm/include/arch/boot/boot.h
similarity index 100%
rename from src/arch/armv7/include/arch/boot/boot.h
rename to src/arch/arm/include/arch/boot/boot.h
diff --git a/src/arch/armv7/include/arch/byteorder.h b/src/arch/arm/include/arch/byteorder.h
similarity index 100%
rename from src/arch/armv7/include/arch/byteorder.h
rename to src/arch/arm/include/arch/byteorder.h
diff --git a/src/arch/armv7/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h
similarity index 100%
rename from src/arch/armv7/include/arch/early_variables.h
rename to src/arch/arm/include/arch/early_variables.h
diff --git a/src/arch/armv7/include/arch/exception.h b/src/arch/arm/include/arch/exception.h
similarity index 100%
rename from src/arch/armv7/include/arch/exception.h
rename to src/arch/arm/include/arch/exception.h
diff --git a/src/arch/armv7/include/arch/hlt.h b/src/arch/arm/include/arch/hlt.h
similarity index 100%
rename from src/arch/armv7/include/arch/hlt.h
rename to src/arch/arm/include/arch/hlt.h
diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/arm/include/arch/io.h
similarity index 83%
rename from src/arch/armv7/include/arch/io.h
rename to src/arch/arm/include/arch/io.h
index e044090..e537297 100644
--- a/src/arch/armv7/include/arch/io.h
+++ b/src/arch/arm/include/arch/io.h
@@ -23,48 +23,9 @@
#ifndef __ASM_ARM_IO_H
#define __ASM_ARM_IO_H
-#include <types.h>
-#include <arch/cache.h> /* for dmb() */
#include <arch/byteorder.h>
-
-static inline uint8_t read8(const void *addr)
-{
- dmb();
- return *(volatile uint8_t *)addr;
-}
-
-static inline uint16_t read16(const void *addr)
-{
- dmb();
- return *(volatile uint16_t *)addr;
-}
-
-static inline uint32_t read32(const void *addr)
-{
- dmb();
- return *(volatile uint32_t *)addr;
-}
-
-static inline void write8(uint8_t val, void *addr)
-{
- dmb();
- *(volatile uint8_t *)addr = val;
- dmb();
-}
-
-static inline void write16(uint16_t val, void *addr)
-{
- dmb();
- *(volatile uint16_t *)addr = val;
- dmb();
-}
-
-static inline void write32(uint32_t val, void *addr)
-{
- dmb();
- *(volatile uint32_t *)addr = val;
- dmb();
-}
+#include <arch/arch_io.h>
+#include <stdint.h>
/*
* FIXME: These are to avoid breaking existing ARM code. We should eventually
diff --git a/src/arch/armv7/include/arch/pci_ops.h b/src/arch/arm/include/arch/pci_ops.h
similarity index 93%
rename from src/arch/armv7/include/arch/pci_ops.h
rename to src/arch/arm/include/arch/pci_ops.h
index 7a7ed32..faa7701 100644
--- a/src/arch/armv7/include/arch/pci_ops.h
+++ b/src/arch/arm/include/arch/pci_ops.h
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef ARCH_ARMV7_PCI_OPS_H
-#define ARCH_ARMV7_PCI_OPS_H
+#ifndef ARCH_ARM_PCI_OPS_H
+#define ARCH_ARM_PCI_OPS_H
/* Empty stub until PCI includes are properly fixed. */
diff --git a/src/arch/armv7/include/arch/stages.h b/src/arch/arm/include/arch/stages.h
similarity index 98%
rename from src/arch/armv7/include/arch/stages.h
rename to src/arch/arm/include/arch/stages.h
index 671c02b..39fed99 100644
--- a/src/arch/armv7/include/arch/stages.h
+++ b/src/arch/arm/include/arch/stages.h
@@ -22,7 +22,7 @@
extern void main(void);
-void stage_entry(void) __attribute__((section(".text.stage_entry.armv7")));
+void stage_entry(void) __attribute__((section(".text.stage_entry.arm")));
void stage_exit(void *);
#endif
diff --git a/src/arch/armv7/include/armv7.h b/src/arch/arm/include/armv7.h
similarity index 100%
rename from src/arch/armv7/include/armv7.h
rename to src/arch/arm/include/armv7.h
diff --git a/src/arch/arm/include/armv7/arch/arch_io.h b/src/arch/arm/include/armv7/arch/arch_io.h
new file mode 100644
index 0000000..360fa64
--- /dev/null
+++ b/src/arch/arm/include/armv7/arch/arch_io.h
@@ -0,0 +1,68 @@
+/*
+ * Originally imported from linux/include/asm-arm/io.h. This file has changed
+ * substantially since then.
+ *
+ * Copyright 2013 Google Inc.
+ * Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ * 08-Apr-2013 G Replaced several macros with inlines for type safety.
+ * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
+ * constant addresses and variable addresses.
+ * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
+ * specific IO header files.
+ * 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
+ * 04-Apr-1999 PJB Added check_signature.
+ * 12-Dec-1999 RMK More cleanups
+ * 18-Jun-2000 RMK Removed virt_to_* and friends definitions
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <arch/cache.h> /* for dmb() */
+#include <stdint.h>
+
+static inline uint8_t read8(const void *addr)
+{
+ dmb();
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const void *addr)
+{
+ dmb();
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const void *addr)
+{
+ dmb();
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(uint8_t val, void *addr)
+{
+ dmb();
+ *(volatile uint8_t *)addr = val;
+ dmb();
+}
+
+static inline void write16(uint16_t val, void *addr)
+{
+ dmb();
+ *(volatile uint16_t *)addr = val;
+ dmb();
+}
+
+static inline void write32(uint32_t val, void *addr)
+{
+ dmb();
+ *(volatile uint32_t *)addr = val;
+ dmb();
+}
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/payloads/libpayload/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
similarity index 97%
copy from payloads/libpayload/include/armv7/arch/cache.h
copy to src/arch/arm/include/armv7/arch/cache.h
index 1cd9958..ffdb55a 100644
--- a/payloads/libpayload/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -26,11 +26,11 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
- * cache.h: Cache maintenance API for ARMv7
+ * cache.h: Cache maintenance API for ARM
*/
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
+#ifndef ARM_CACHE_H
+#define ARM_CACHE_H
#include <stddef.h>
#include <stdint.h>
@@ -320,8 +320,8 @@
* Generalized setup/init functions
*/
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
+/* invalidate all caches on ARM */
+void arm_invalidate_caches(void);
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
@@ -338,4 +338,4 @@
void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
enum dcache_policy policy);
-#endif /* ARMV7_CACHE_H */
+#endif /* ARM_CACHE_H */
diff --git a/src/arch/armv7/include/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h
similarity index 100%
rename from src/arch/armv7/include/arch/cpu.h
rename to src/arch/arm/include/armv7/arch/cpu.h
diff --git a/src/arch/armv7/include/arch/types.h b/src/arch/arm/include/armv7/arch/types.h
similarity index 100%
rename from src/arch/armv7/include/arch/types.h
rename to src/arch/arm/include/armv7/arch/types.h
diff --git a/src/arch/armv7/include/assembler.h b/src/arch/arm/include/assembler.h
similarity index 100%
rename from src/arch/armv7/include/assembler.h
rename to src/arch/arm/include/assembler.h
diff --git a/src/arch/armv7/include/bootblock_common.h b/src/arch/arm/include/bootblock_common.h
similarity index 100%
rename from src/arch/armv7/include/bootblock_common.h
rename to src/arch/arm/include/bootblock_common.h
diff --git a/src/arch/armv7/include/clocks.h b/src/arch/arm/include/clocks.h
similarity index 100%
rename from src/arch/armv7/include/clocks.h
rename to src/arch/arm/include/clocks.h
diff --git a/src/arch/armv7/include/smp/spinlock.h b/src/arch/arm/include/smp/spinlock.h
similarity index 100%
rename from src/arch/armv7/include/smp/spinlock.h
rename to src/arch/arm/include/smp/spinlock.h
diff --git a/src/arch/armv7/include/stdint.h b/src/arch/arm/include/stdint.h
similarity index 100%
rename from src/arch/armv7/include/stdint.h
rename to src/arch/arm/include/stdint.h
diff --git a/src/arch/armv7/include/utils.h b/src/arch/arm/include/utils.h
similarity index 100%
rename from src/arch/armv7/include/utils.h
rename to src/arch/arm/include/utils.h
diff --git a/src/arch/armv7/memcpy.S b/src/arch/arm/memcpy.S
similarity index 100%
rename from src/arch/armv7/memcpy.S
rename to src/arch/arm/memcpy.S
diff --git a/src/arch/armv7/memmove.S b/src/arch/arm/memmove.S
similarity index 100%
rename from src/arch/armv7/memmove.S
rename to src/arch/arm/memmove.S
diff --git a/src/arch/armv7/memset.S b/src/arch/arm/memset.S
similarity index 100%
rename from src/arch/armv7/memset.S
rename to src/arch/arm/memset.S
diff --git a/src/arch/armv7/ramstage.ld b/src/arch/arm/ramstage.ld
similarity index 98%
rename from src/arch/armv7/ramstage.ld
rename to src/arch/arm/ramstage.ld
index 91efe2c..cab512e 100644
--- a/src/arch/armv7/ramstage.ld
+++ b/src/arch/arm/ramstage.ld
@@ -38,7 +38,7 @@
.text : {
_text = .;
_start = .;
- *(.text.stage_entry.armv7);
+ *(.text.stage_entry.arm);
*(.text);
*(.text.*);
. = ALIGN(16);
diff --git a/src/arch/armv7/romstage.ld b/src/arch/arm/romstage.ld
similarity index 98%
rename from src/arch/armv7/romstage.ld
rename to src/arch/arm/romstage.ld
index a9c3f8b..65b133a 100644
--- a/src/arch/armv7/romstage.ld
+++ b/src/arch/arm/romstage.ld
@@ -41,7 +41,7 @@
.romtext . : {
_rom = .;
_start = .;
- *(.text.stage_entry.armv7);
+ *(.text.stage_entry.arm);
*(.text.startup);
*(.text);
} : to_load
diff --git a/src/arch/armv7/stages.c b/src/arch/arm/stages.c
similarity index 100%
rename from src/arch/armv7/stages.c
rename to src/arch/arm/stages.c
diff --git a/src/arch/armv7/tables.c b/src/arch/arm/tables.c
similarity index 100%
rename from src/arch/armv7/tables.c
rename to src/arch/arm/tables.c
diff --git a/src/arch/armv7/include/arch/cache.h b/src/arch/armv7/include/arch/cache.h
deleted file mode 100644
index 1cd9958..0000000
--- a/src/arch/armv7/include/arch/cache.h
+++ /dev/null
@@ -1,341 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- * derived from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * cache.h: Cache maintenance API for ARMv7
- */
-
-#ifndef ARMV7_CACHE_H
-#define ARMV7_CACHE_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-/* SCTLR bits */
-#define SCTLR_M (1 << 0) /* MMU enable */
-#define SCTLR_A (1 << 1) /* Alignment check enable */
-#define SCTLR_C (1 << 2) /* Data/unified cache enable */
-/* Bits 4:3 are reserved */
-#define SCTLR_CP15BEN (1 << 5) /* CP15 barrier enable */
-/* Bit 6 is reserved */
-#define SCTLR_B (1 << 7) /* Endianness */
-/* Bits 9:8 */
-#define SCTLR_SW (1 << 10) /* SWP and SWPB enable */
-#define SCTLR_Z (1 << 11) /* Branch prediction enable */
-#define SCTLR_I (1 << 12) /* Instruction cache enable */
-#define SCTLR_V (1 << 13) /* Low/high exception vectors */
-#define SCTLR_RR (1 << 14) /* Round Robin select */
-/* Bits 16:15 are reserved */
-#define SCTLR_HA (1 << 17) /* Hardware Access flag enable */
-/* Bit 18 is reserved */
-/* Bits 20:19 reserved virtualization not supported */
-#define SCTLR_WXN (1 << 19) /* Write permission implies XN */
-#define SCTLR_UWXN (1 << 20) /* Unprivileged write permission
- implies PL1 XN */
-#define SCTLR_FI (1 << 21) /* Fast interrupt config enable */
-#define SCTLR_U (1 << 22) /* Unaligned access behavior */
-#define SCTLR_VE (1 << 24) /* Interrupt vectors enable */
-#define SCTLR_EE (1 << 25) /* Exception endianness */
-/* Bit 26 is reserved */
-#define SCTLR_NMFI (1 << 27) /* Non-maskable FIQ support */
-#define SCTLR_TRE (1 << 28) /* TEX remap enable */
-#define SCTLR_AFE (1 << 29) /* Access flag enable */
-#define SCTLR_TE (1 << 30) /* Thumb exception enable */
-/* Bit 31 is reserved */
-
-/*
- * Sync primitives
- */
-
-/* data memory barrier */
-static inline void dmb(void)
-{
- asm volatile ("dmb" : : : "memory");
-}
-
-/* data sync barrier */
-static inline void dsb(void)
-{
- asm volatile ("dsb" : : : "memory");
-}
-
-/* instruction sync barrier */
-static inline void isb(void)
-{
- asm volatile ("isb" : : : "memory");
-}
-
-/*
- * Low-level TLB maintenance operations
- */
-
-/* invalidate entire data TLB */
-static inline void dtlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate entire instruction TLB */
-static inline void itlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
-}
-
-/* invalidate entire unified TLB */
-static inline void tlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate unified TLB by MVA, all ASID */
-static inline void tlbimvaa(unsigned long mva)
-{
- asm volatile ("mcr p15, 0, %0, c8, c7, 3" : : "r" (mva) : "memory");
-}
-
-/* write data access control register (DACR) */
-static inline void write_dacr(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c3, c0, 0" : : "r" (val));
-}
-
-/* write translation table base register 0 (TTBR0) */
-static inline void write_ttbr0(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c2, c0, 0" : : "r" (val) : "memory");
-}
-
-/* read translation table base control register (TTBCR) */
-static inline uint32_t read_ttbcr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 0, %0, c2, c0, 2" : "=r" (val));
- return val;
-}
-
-/* write translation table base control register (TTBCR) */
-static inline void write_ttbcr(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c2, c0, 2" : : "r" (val) : "memory");
-}
-
-/*
- * Low-level cache maintenance operations
- */
-
-/* branch predictor invalidate all */
-static inline void bpiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
-}
-
-/* data cache clean and invalidate by MVA to PoC */
-static inline void dccimvac(unsigned long mva)
-{
- asm volatile ("mcr p15, 0, %0, c7, c14, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dccisw(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c7, c14, 2" : : "r" (val) : "memory");
-}
-
-/* data cache clean by MVA to PoC */
-static inline void dccmvac(unsigned long mva)
-{
- asm volatile ("mcr p15, 0, %0, c7, c10, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache clean by set/way */
-static inline void dccsw(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c7, c10, 2" : : "r" (val) : "memory");
-}
-
-/* data cache invalidate by MVA to PoC */
-static inline void dcimvac(unsigned long mva)
-{
- asm volatile ("mcr p15, 0, %0, c7, c6, 1" : : "r" (mva) : "memory");
-}
-
-/* data cache invalidate by set/way */
-static inline void dcisw(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c7, c6, 2" : : "r" (val) : "memory");
-}
-
-/* instruction cache invalidate all by PoU */
-static inline void iciallu(void)
-{
- asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0));
-}
-
-/*
- * Cache co-processor (CP15) access functions
- */
-
-/* read cache level ID register (CLIDR) */
-static inline uint32_t read_clidr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 1, %0, c0, c0, 1" : "=r" (val));
- return val;
-}
-
-/* read cache size ID register register (CCSIDR) */
-static inline uint32_t read_ccsidr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
- return val;
-}
-
-/* read cache size selection register (CSSELR) */
-static inline uint32_t read_csselr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 2, %0, c0, c0, 0" : "=r" (val));
- return val;
-}
-
-/* write to cache size selection register (CSSELR) */
-static inline void write_csselr(uint32_t val)
-{
- /*
- * Bits [3:1] - Cache level + 1 (0b000 = L1, 0b110 = L7, 0b111 is rsvd)
- * Bit 0 - 0 = data or unified cache, 1 = instruction cache
- */
- asm volatile ("mcr p15, 2, %0, c0, c0, 0" : : "r" (val));
- isb(); /* ISB to sync the change to CCSIDR */
-}
-
-/* read L2 control register (L2CTLR) */
-static inline uint32_t read_l2ctlr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
- return val;
-}
-
-/* write L2 control register (L2CTLR) */
-static inline void write_l2ctlr(uint32_t val)
-{
- /*
- * Note: L2CTLR can only be written when the L2 memory system
- * is idle, ie before the MMU is enabled.
- */
- asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory" );
- isb();
-}
-
-/* read L2 Auxiliary Control Register (L2ACTLR) */
-static inline uint32_t read_l2actlr(void)
-{
- uint32_t val = 0;
- asm volatile ("mrc p15, 1, %0, c15, c0, 0" : "=r" (val));
- return val;
-}
-
-/* write L2 Auxiliary Control Register (L2ACTLR) */
-static inline void write_l2actlr(uint32_t val)
-{
- asm volatile ("mcr p15, 1, %0, c15, c0, 0" : : "r" (val) : "memory" );
- isb();
-}
-
-/* read system control register (SCTLR) */
-static inline uint32_t read_sctlr(void)
-{
- uint32_t val;
- asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (val));
- return val;
-}
-
-/* write system control register (SCTLR) */
-static inline void write_sctlr(uint32_t val)
-{
- asm volatile ("mcr p15, 0, %0, c1, c0, 0" : : "r" (val) : "cc");
- isb();
-}
-
-/*
- * Cache maintenance API
- */
-
-/* dcache clean and invalidate all (on current level given by CCSELR) */
-void dcache_clean_invalidate_all(void);
-
-/* dcache clean by modified virtual address to PoC */
-void dcache_clean_by_mva(void const *addr, size_t len);
-
-/* dcache clean and invalidate by modified virtual address to PoC */
-void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
-
-/* dcache invalidate by modified virtual address to PoC */
-void dcache_invalidate_by_mva(void const *addr, size_t len);
-
-void dcache_clean_all(void);
-
-/* dcache invalidate all (on current level given by CCSELR) */
-void dcache_invalidate_all(void);
-
-/* dcache and MMU disable */
-void dcache_mmu_disable(void);
-
-/* dcache and MMU enable */
-void dcache_mmu_enable(void);
-
-/* icache invalidate all (on current level given by CSSELR) */
-void icache_invalidate_all(void);
-
-/* tlb invalidate all */
-void tlb_invalidate_all(void);
-
-/*
- * Generalized setup/init functions
- */
-
-/* invalidate all caches on ARMv7 */
-void armv7_invalidate_caches(void);
-
-/* mmu initialization (set page table address, set permissions, etc) */
-void mmu_init(void);
-
-enum dcache_policy {
- DCACHE_OFF,
- DCACHE_WRITEBACK,
- DCACHE_WRITETHROUGH,
-};
-
-/* disable the mmu for a range. Primarily useful to lock out address 0. */
-void mmu_disable_range(unsigned long start_mb, unsigned long size_mb);
-/* mmu range configuration (set dcache policy) */
-void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
- enum dcache_policy policy);
-
-#endif /* ARMV7_CACHE_H */
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 054177f..c7c3ea5 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -2,7 +2,7 @@
config BOOTBLOCK_CONSOLE
bool "Enable early (bootblock) console output."
- depends on ARCH_ARMV7
+ depends on ARCH_ARM
default n
help
Use console during the bootblock if supported
diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc
index c5c1e64..032b1f4 100644
--- a/src/cpu/ti/am335x/Makefile.inc
+++ b/src/cpu/ti/am335x/Makefile.inc
@@ -16,7 +16,7 @@
endif
$(call add-class,omap-header)
-$(eval $(call create_class_compiler,omap-header,armv7))
+$(eval $(call create_class_compiler,omap-header,arm))
real-target: $(obj)/MLO
diff --git a/src/device/oprom/yabel/device.h b/src/device/oprom/yabel/device.h
index 017aab9..63f1d8e 100644
--- a/src/device/oprom/yabel/device.h
+++ b/src/device/oprom/yabel/device.h
@@ -128,7 +128,7 @@
static inline void
out32le(void *addr, u32 val)
{
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
*((u32*) addr) = cpu_to_le32(val);
#else
asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
@@ -139,7 +139,7 @@
in32le(void *addr)
{
u32 val;
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
val = cpu_to_le32(*((u32 *) addr));
#else
asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
@@ -150,7 +150,7 @@
static inline void
out16le(void *addr, u16 val)
{
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
*((u16*) addr) = cpu_to_le16(val);
#else
asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
@@ -161,7 +161,7 @@
in16le(void *addr)
{
u16 val;
-#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARMV7
+#if CONFIG_ARCH_X86 || CONFIG_ARCH_ARM
val = cpu_to_le16(*((u16*) addr));
#else
asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig
index a979437..fef745e 100644
--- a/src/drivers/uart/Kconfig
+++ b/src/drivers/uart/Kconfig
@@ -5,7 +5,7 @@
config DRIVERS_UART_8250IO
bool "Serial port on SuperIO"
- depends on !ARCH_ARMV7
+ depends on !ARCH_ARM
default n if NO_UART_ON_SUPERIO
default y if ARCH_X86
diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h
index a1d8127..e74d618 100644
--- a/src/include/cbfs_core.h
+++ b/src/include/cbfs_core.h
@@ -107,7 +107,7 @@
*/
#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
#define CBFS_ARCHITECTURE_X86 0x00000001
-#define CBFS_ARCHITECTURE_ARMV7 0x00000010
+#define CBFS_ARCHITECTURE_ARM 0x00000010
/** This is a component header - every entry in the CBFS
will have this header.
diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S
index 8d0beb8..5f7de13 100644
--- a/src/soc/nvidia/tegra124/bootblock_asm.S
+++ b/src/soc/nvidia/tegra124/bootblock_asm.S
@@ -1,5 +1,5 @@
/*
- * Early initialization code for ARMv7 architecture.
+ * Early initialization code for ARM architecture.
*
* This file is based off of the OMAP3530/ARM Cortex start.S file from Das
* U-Boot, which itself got the file from armboot.
diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c
index e0ec30b..bc56a19 100644
--- a/src/vendorcode/google/chromeos/fmap.c
+++ b/src/vendorcode/google/chromeos/fmap.c
@@ -41,7 +41,7 @@
/* wrapping around 0x100000000 */
const struct fmap *fmap = (void *)
(CONFIG_FLASHMAP_OFFSET - CONFIG_ROM_SIZE);
-#elif CONFIG_ARCH_ARMV7
+#elif CONFIG_ARCH_ARM
struct cbfs_media default_media, *media;
media = &default_media;
init_default_cbfs_media(media);
diff --git a/toolchain.inc b/toolchain.inc
index 3b9c5d2..326e474 100644
--- a/toolchain.inc
+++ b/toolchain.inc
@@ -55,12 +55,9 @@
ARCHDIR-i386 := x86
ARCHDIR-x86_32 := x86
-ARCHDIR-armv7 := armv7
+ARCHDIR-arm := arm
-CFLAGS_armv7 += \
- -ffixed-r8\
- -march=armv7-a\
- -marm\
+CFLAGS_arm += \
-mno-unaligned-access\
-mthumb\
-mthumb-interwork
diff --git a/util/cbfstool/cbfs.h b/util/cbfstool/cbfs.h
index 52a4a50..6a54bc8 100644
--- a/util/cbfstool/cbfs.h
+++ b/util/cbfstool/cbfs.h
@@ -51,7 +51,7 @@
#define CBFS_ARCHITECTURE_UNKNOWN 0xFFFFFFFF
#define CBFS_ARCHITECTURE_X86 0x00000001
-#define CBFS_ARCHITECTURE_ARMV7 0x00000010
+#define CBFS_ARCHITECTURE_ARM 0x00000010
#define CBFS_FILE_MAGIC "LARCHIVE"
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index f236d8b..937b610 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -586,7 +586,7 @@
"Updates the FIT table with microcode entries\n"
"\n"
"ARCHes:\n"
- " armv7, x86\n"
+ " arm, x86\n"
"TYPEs:\n", name, name
);
print_supported_filetypes();
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 6778eb9..a28e741 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -130,7 +130,7 @@
uint32_t arch;
const char *name;
} arch_names[] = {
- { CBFS_ARCHITECTURE_ARMV7, "armv7" },
+ { CBFS_ARCHITECTURE_ARM, "arm" },
{ CBFS_ARCHITECTURE_X86, "x86" },
{ CBFS_ARCHITECTURE_UNKNOWN, "unknown" }
};
diff --git a/util/cbfstool/elfheaders.c b/util/cbfstool/elfheaders.c
index fdd1599..4c0de89 100644
--- a/util/cbfstool/elfheaders.c
+++ b/util/cbfstool/elfheaders.c
@@ -610,7 +610,7 @@
// The tool may work in architecture-independent way.
if (arch != CBFS_ARCHITECTURE_UNKNOWN &&
- !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARMV7)) &&
+ !((ehdr->e_machine == EM_ARM) && (arch == CBFS_ARCHITECTURE_ARM)) &&
!((ehdr->e_machine == EM_386) && (arch == CBFS_ARCHITECTURE_X86))) {
ERROR("The stage file has the wrong architecture\n");
return -1;
diff --git a/util/runfw/googlesnow.c b/util/runfw/googlesnow.c
index 686b4bc..125e0a2 100644
--- a/util/runfw/googlesnow.c
+++ b/util/runfw/googlesnow.c
@@ -114,7 +114,7 @@
1: x/i $pc
=> 0x20234bc <call_bootblock+12>: blx 0x20244b8 <main>
(gdb)
-main (bist=0) at src/arch/armv7/bootblock_simple.c:37
+main (bist=0) at src/arch/arm/bootblock_simple.c:37
37 {
1: x/i $pc
=> 0x20244b8 <main>: push {r3, lr}
diff --git a/util/showdevicetree/showdt.c b/util/showdevicetree/showdt.c
index dc4e4d6..4e904a2 100644
--- a/util/showdevicetree/showdt.c
+++ b/util/showdevicetree/showdt.c
@@ -165,5 +165,5 @@
* Example: (yank this and paste into M-x compile in emacs)
* or tail -2 showdt.c | head -1 |sh
* or whatever.
- cc -I ../src -I ../src/include -I ../src/arch/armv7/include/ -include build/mainboard/google/snow/static.c showdt.c
+ cc -I ../src -I ../src/include -I ../src/arch/arm/include/ -include build/mainboard/google/snow/static.c showdt.c
*/
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 4b18942..e9f6d326 100755
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -167,10 +167,10 @@
}
# Architecture definition
-SUPPORTED_ARCHITECTURE="x86 armv7 aarch64"
+SUPPORTED_ARCHITECTURE="x86 arm aarch64"
-arch_config_armv7() {
- TARCH="armv7"
+arch_config_arm() {
+ TARCH="arm"
TBFDARCH="littlearm"
TCLIST="armv7a armv7-a"
TWIDTH="32"