diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index 87fc4711..626d735 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -1005,6 +1005,169 @@
 		{ 0x1fc, "MSR_POWER_CTL" },
 	};
 
+/*
+ * The following two tables are the Silvermont registers listed in Table 35-6
+ * Intel® 64 and IA-32 Architectures Software Developer’s Manual
+ * September 2014
+ * Vol. 3C 35-59
+ */
+	static const msr_entry_t silvermont_per_core_msrs[] = {
+		/*
+		 * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture
+		 * These are MSRs marked as "core"
+		 *
+		 */
+		{ 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" },
+		{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
+		{ 0x001b, "IA32_APIC_BASE" },
+		{ 0x0034, "MSR_SMI_COUNT" },
+		{ 0x003a, "IA32_FEATURE_CONTROL" },
+		{ 0x0040, "MSR_LASTBRANCH_0_FROM_IP" },
+		{ 0x0041, "MSR_LASTBRANCH_1_FROM_IP" },
+		{ 0x0042, "MSR_LASTBRANCH_2_FROM_IP" },
+		{ 0x0043, "MSR_LASTBRANCH_3_FROM_IP" },
+		{ 0x0044, "MSR_LASTBRANCH_4_FROM_IP" },
+		{ 0x0045, "MSR_LASTBRANCH_5_FROM_IP" },
+		{ 0x0046, "MSR_LASTBRANCH_6_FROM_IP" },
+		{ 0x0047, "MSR_LASTBRANCH_7_FROM_IP" },
+		{ 0x0060, "MSR_LASTBRANCH_0_TO_IP" },
+		{ 0x0061, "MSR_LASTBRANCH_1_TO_IP" },
+		{ 0x0062, "MSR_LASTBRANCH_2_TO_IP" },
+		{ 0x0063, "MSR_LASTBRANCH_3_TO_IP" },
+		{ 0x0064, "MSR_LASTBRANCH_4_TO_IP" },
+		{ 0x0065, "MSR_LASTBRANCH_5_TO_IP" },
+		{ 0x0066, "MSR_LASTBRANCH_6_TO_IP" },
+		{ 0x0067, "MSR_LASTBRANCH_7_TO_IP" },
+		/* Write register
+		{ 0x0079, "IA32_BIOS_UPDT_TRIG" },
+		*/
+		{ 0x008b, "IA32_BIOS_SIGN_ID" },
+		{ 0x00c1, "IA32_PMC0" },
+		{ 0x00c2, "IA32_PMC1" },
+		{ 0x00e7, "IA32_MPERF" },
+		{ 0x00e8, "IA32_APERF" },
+		{ 0x00fe, "IA32_MTRRCAP" },
+		{ 0x0174, "IA32_SYSENTER_CS" },
+		{ 0x0175, "IA32_SYSENTER_ESP" },
+		{ 0x0176, "IA32_SYSENTER_EIP" },
+		{ 0x0179, "IA32_MCG_CAP" },
+		{ 0x017a, "IA32_MCG_STATUS" },
+		{ 0x0186, "IA32_PERF_EVNTSEL0" },
+		{ 0x0187, "IA32_PERF_EVNTSEL1" },
+		{ 0x0199, "IA32_PERF_CONTROL" },
+		{ 0x019a, "IA32_CLOCK_MODULATION" },
+		{ 0x019b, "IA32_THERM_INTERRUPT" },
+		{ 0x019c, "IA32_THERM_STATUS" },
+		{ 0x01a0, "IA32_MISC_ENABLES" },
+		{ 0x01b0, "IA32_ENERGY_PERF_BIAS" },
+		{ 0x01c9, "MSR_LASTBRANCH_TOS" },
+		{ 0x01d9, "IA32_DEBUGCTL" },
+		{ 0x01dd, "MSR_LER_FROM_LIP" },
+		{ 0x01de, "MSR_LER_TO_LIP" },
+		{ 0x01f2, "IA32_SMRR_PHYSBASE" },
+		{ 0x01f3, "IA32_SMRR_PHYSMASK" },
+		{ 0x0200, "IA32_MTRR_PHYSBASE0" },
+		{ 0x0201, "IA32_MTRR_PHYSMASK0" },
+		{ 0x0202, "IA32_MTRR_PHYSBASE1" },
+		{ 0x0203, "IA32_MTRR_PHYSMASK1" },
+		{ 0x0204, "IA32_MTRR_PHYSBASE2" },
+		{ 0x0205, "IA32_MTRR_PHYSMASK2" },
+		{ 0x0206, "IA32_MTRR_PHYSBASE3" },
+		{ 0x0207, "IA32_MTRR_PHYSMASK3" },
+		{ 0x0208, "IA32_MTRR_PHYSBASE4" },
+		{ 0x0209, "IA32_MTRR_PHYSMASK4" },
+		{ 0x020a, "IA32_MTRR_PHYSBASE5" },
+		{ 0x020b, "IA32_MTRR_PHYSMASK5" },
+		{ 0x020c, "IA32_MTRR_PHYSBASE6" },
+		{ 0x020d, "IA32_MTRR_PHYSMASK6" },
+		{ 0x020e, "IA32_MTRR_PHYSBASE7" },
+		{ 0x020f, "IA32_MTRR_PHYSMASK7" },
+		{ 0x0250, "IA32_MTRR_FIX64K_00000" },
+		{ 0x0258, "IA32_MTRR_FIX16K_80000" },
+		{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
+		{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
+		{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
+		{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
+		{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
+		{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
+		{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
+		{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
+		{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
+		{ 0x0277, "IA32_PAT" },
+		{ 0x02FF, "IA32_MTRR_DEF_TYPE" },
+		{ 0x0309, "IA32_FIXED_CTR0" },
+		{ 0x030a, "IA32_FIXED_CTR1" },
+		{ 0x030b, "IA32_FIXED_CTR2" },
+		{ 0x0345, "IA32_PERF_CAPABILITIES" },
+		{ 0x038d, "IA32_FIXED_CTR_CTRL" },
+		{ 0x038e, "IA32_PERF_GLOBAL_STATUS" },
+		{ 0x038f, "IA32_PERF_GLOBAL_CTRL" },
+		{ 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" },
+		{ 0x03f1, "MSR_PEBS_ENABLE" },
+		{ 0x03fd, "MSR_CORE_C6_RESIDENCY" },
+		{ 0x40c, "IA32_MC3_CTL" },
+		{ 0x40d, "IA32_MC3_STATUS" },
+		{ 0x40e, "IA32_MC3_ADDR" },
+		{ 0x410, "IA32_MC4_CTL" },
+		{ 0x411, "IA32_MC4_STATUS" },
+		{ 0x412, "IA32_MC4_ADDR" },
+		{ 0x0480, "IA32_VMX_BASIC" },
+		{ 0x0481, "IA32_VMX_PINBASED_CTLS" },
+		{ 0x0482, "IA32_VMX_PROCBASED_CTLS" },
+		{ 0x0483, "IA32_VMX_EXIT_CTLS" },
+		{ 0x0484, "IA32_VMX_ENTRY_CTLS" },
+		{ 0x0485, "IA32_VMX_MISC" },
+		{ 0x0486, "IA32_VMX_CR0_FIXED0" },
+		{ 0x0487, "IA32_VMX_CR0_FIXED1" },
+		{ 0x0488, "IA32_VMX_CR4_FIXED0" },
+		{ 0x0489, "IA32_VMX_CR4_FIXED1" },
+		{ 0x048a, "IA32_VMX_VMCS_ENUM" },
+		{ 0x048b, "IA32_VMX_PROCBASED_CTLS2" },
+		{ 0x048c, "IA32_VMX_EPT_VPID_ENUM" },
+		{ 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" },
+		{ 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" },
+		{ 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" },
+		{ 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" },
+		{ 0x0491, "IA32_VMX_FMFUNC" },
+		{ 0x04c1, "IA32_A_PMC0" },
+		{ 0x04c2, "IA32_A_PMC1" },
+		{ 0x0600, "IA32_DS_AREA" },
+		{ 0x0660, "MSR_CORE_C1_RESIDENCY" },
+		{ 0x06e0, "IA32_TSC_DEADLINE" },
+	};
+
+	static const msr_entry_t silvermont_global_msrs[] = {
+		/*
+		 * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture
+		 * These are MSRs marked as "shared" or "package"
+		 */
+		{ 0x0000, "IA32_P5_MC_ADDR" },
+		{ 0x0001, "IA32_P5_MC_TYPE" },
+		{ 0x0017, "IA32_PLATFORM_ID" },
+		{ 0x002a, "MSR_EBC_HARD_POWERON" },
+		{ 0x00cd, "MSR_FSB_FREQ" },
+		{ 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" },
+		{ 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" },
+		{ 0x011e, "BBL_CR_CTL3" },
+		{ 0x0198, "IA32_PERF_STATUS" },
+		{ 0x01A2, "MSR_TEMPERATURE_TARGET" },
+		{ 0x01A6, "MSR_OFFCORE_RSP_0" },
+		{ 0x01A7, "MSR_OFFCORE_RSP_1" },
+		{ 0x01AD, "MSR_TURBO_RATIO_LIMIT" },
+		{ 0x03fa, "MSR_PKG_C6_RESIDENCY" },
+		{ 0x400, "IA32_MC0_CTL" },
+		{ 0x401, "IA32_MC0_STATUS" },
+		{ 0x402, "IA32_MC0_ADDR" },
+		{ 0x404, "IA32_MC1_CTL" },
+		{ 0x405, "IA32_MC1_STATUS" },
+		{ 0x408, "IA32_MC2_CTL" },
+		{ 0x409, "IA32_MC2_STATUS" },
+		{ 0x40a, "IA32_MC2_ADDR" },
+		{ 0x414, "MSR_MC5_CTL" },
+		{ 0x415, "MSR_MC5_STATUS" },
+		{ 0x416, "MSR_MC5_ADDR" },
+	};
+
 	typedef struct {
 		unsigned int model;
 		const msr_entry_t *global_msrs;
@@ -1022,6 +1185,9 @@
 		{ 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) },
 		{ 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) },
 		{ 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) },
+
+		{ CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */
+
 	};
 
 	cpu_t *cpu = NULL;