mb/*: Add consolidated USB port config for SNB+MRC boards
For each sandybridge boards with option to use MRC or native platform
init code, add a copy of the board's USB port config, consolidated between
both code paths, into the southbridge devicetree, using special values
allocated for this consolidation.
These get hooked up in a separate patch.
Change-Id: I53efca3d29b3c5d4d5b7e3d6dc3e6ce6c34201e6
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81880
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index f4e948f..8b10b6b 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -43,6 +43,23 @@
register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff
+ register "usb_port_config" = "{
+ {1, 1, 0}, /* back, towards HDMI plugs */
+ {1, 1, 0}, /* back, towards power plug */
+ {1, 1, 1}, /* half-width miniPCIe */
+ {1, 1, 1}, /* full-width miniPCIe */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 2}, /* front-panel header */
+ {1, 1, 3}, /* front connector */
+ {0, 1, 3}, /* not available x7 */
+ {0, 1, 4},
+ {0, 1, 4},
+ {0, 1, 5},
+ {0, 1, 5},
+ {0, 1, 6},
+ {0, 1, 6}
+ }"
+
device ref xhci off end # USB xHCI
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index e75505e..75e6daa 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -58,6 +58,22 @@
register "gen2_dec" = "0x000c0181"
# SuperIO range is 0x700-0x73f
register "gen3_dec" = "0x003c0701"
+ register "usb_port_config" = "{
+ { 1, 0, 0 }, /* P0: Front port (OC0) */
+ { 1, 0, 1 }, /* P1: Back port (OC1) */
+ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */
+ { 1, 0, -1 }, /* P3: MMC (no OC) */
+ { 1, 0, 2 }, /* P4: Front port (OC2) */
+ { 0, 0, -1 }, /* P5: Empty */
+ { 0, 0, -1 }, /* P6: Empty */
+ { 0, 0, -1 }, /* P7: Empty */
+ { 1, 0, 4 }, /* P8: Back port (OC4) */
+ { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */
+ { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */
+ { 0, 0, -1 }, /* P11: Empty */
+ { 1, 0, 6 }, /* P12: Back port (OC6) */
+ { 1, 0, 5 }, /* P13: Back port (OC5) */
+ }"
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2