diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
index 186aadb..2b73ad2 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
+++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb
@@ -1,9 +1,9 @@
 chip soc/intel/alderlake
 
 	# GPE configuration
-	register "pmc_gpe0_dw0" = "GPP_A"
-	register "pmc_gpe0_dw1" = "GPP_E"
-	register "pmc_gpe0_dw2" = "GPP_F"
+	register "pmc_gpe0_dw0" = "GPP_B"
+	register "pmc_gpe0_dw1" = "GPP_D"
+	register "pmc_gpe0_dw2" = "GPP_E"
 
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
index 794394f..54321e5 100644
--- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
+++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h
@@ -8,13 +8,13 @@
 
 /* eSPI virtual wire reporting */
 #define EC_SCI_GPI		GPE0_ESPI
-/* EC wake is EC_PCH_INT which is routed to GPP_F17 pin */
-#define GPE_EC_WAKE		GPE0_DW2_17
+/* EC wake is EC_PCH_INT which is routed to GPP_D1 pin */
+#define GPE_EC_WAKE		GPE0_DW1_01
 /* WP signal to PCH */
-#define GPIO_PCH_WP		GPP_E15
+#define GPIO_PCH_WP		GPP_E8
 /* Used to gate SoC's SLP_S0# signal */
-#define GPIO_SLP_S0_GATE	GPP_F9
+#define GPIO_SLP_S0_GATE	GPP_D17
 /* GPIO IRQ for tight timestamps / wake support */
-#define EC_SYNC_IRQ		GPP_F17_IRQ
+#define EC_SYNC_IRQ		GPP_D1_IRQ
 
 #endif /* __BASEBOARD_GPIO_H__ */