skylake/mainboard: Define mainboard hook in bootblock
Move mainboard post console init functionality (google_chrome_ec_init &
early_gpio programming) from verstage to bootblock.
Add chromeos-ec support in bootblock
BUG=chrome-os-partner:55357
BRANCH=none
TEST=Built and boot kunimitsu till POST code 0x34
Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/15786
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 0fee12a..68afb8a 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -25,4 +25,5 @@
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += vtxprintf.c printk.c
bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += init.c console.c
+bootblock-y += post.c
bootblock-y += die.c
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
index c4b9c1a..aeb950f 100644
--- a/src/ec/google/chromeec/Makefile.inc
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -1,6 +1,8 @@
ifeq ($(CONFIG_EC_GOOGLE_CHROMEEC),y)
+bootblock-y += ec.c
bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
+bootblock-$(CONFIG_EC_GOOGLE_CHROMEEC_MEC) += ec_mec.c
ramstage-y += ec.c crosec_proto.c vstore.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_I2C) += ec_i2c.c
ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC_LPC) += ec_lpc.c
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 24116e9..5f708a6 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -201,6 +201,7 @@
$(call src-to-obj,verstage,$(dir)/fmap.c) : $(obj)/fmap_config.h
$(call src-to-obj,postcar,$(dir)/fmap.c) : $(obj)/fmap_config.h
+bootblock-y += bootmode.c
romstage-y += bootmode.c
ramstage-y += bootmode.c
verstage-y += bootmode.c
diff --git a/src/mainboard/google/chell/Makefile.inc b/src/mainboard/google/chell/Makefile.inc
index c0ca567..e52eb7e 100644
--- a/src/mainboard/google/chell/Makefile.inc
+++ b/src/mainboard/google/chell/Makefile.inc
@@ -15,10 +15,12 @@
subdirs-y += spd
+bootblock-y += bootblock_mainboard.c
+
romstage-y += boardid.c
-romstage-y += car.c
romstage-y += pei_data.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -31,5 +33,3 @@
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-verstage-y += car.c
diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/chell/bootblock_mainboard.c
similarity index 87%
rename from src/mainboard/google/chell/car.c
rename to src/mainboard/google/chell/bootblock_mainboard.c
index 7791b92..d5146224 100644
--- a/src/mainboard/google/chell/car.c
+++ b/src/mainboard/google/chell/bootblock_mainboard.c
@@ -13,20 +13,20 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
+ * which it shouldn't do. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
-void car_mainboard_post_console_init(void)
+void bootblock_mainboard_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
diff --git a/src/mainboard/google/glados/Makefile.inc b/src/mainboard/google/glados/Makefile.inc
index c0ca567..e52eb7e 100644
--- a/src/mainboard/google/glados/Makefile.inc
+++ b/src/mainboard/google/glados/Makefile.inc
@@ -15,10 +15,12 @@
subdirs-y += spd
+bootblock-y += bootblock_mainboard.c
+
romstage-y += boardid.c
-romstage-y += car.c
romstage-y += pei_data.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -31,5 +33,3 @@
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-verstage-y += car.c
diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/glados/bootblock_mainboard.c
similarity index 87%
copy from src/mainboard/google/chell/car.c
copy to src/mainboard/google/glados/bootblock_mainboard.c
index 7791b92..d5146224 100644
--- a/src/mainboard/google/chell/car.c
+++ b/src/mainboard/google/glados/bootblock_mainboard.c
@@ -13,20 +13,20 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
+ * which it shouldn't do. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
-void car_mainboard_post_console_init(void)
+void bootblock_mainboard_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
diff --git a/src/mainboard/google/glados/car.c b/src/mainboard/google/glados/car.c
deleted file mode 100644
index 7791b92..0000000
--- a/src/mainboard/google/glados/car.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void car_mainboard_post_console_init(void)
-{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
- early_config_gpio();
-}
diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc
index 4bf6e0a..cafa12c 100644
--- a/src/mainboard/google/lars/Makefile.inc
+++ b/src/mainboard/google/lars/Makefile.inc
@@ -16,10 +16,12 @@
subdirs-y += spd
+bootblock-y += bootblock_mainboard.c
+
romstage-y += boardid.c
-romstage-y += car.c
romstage-y += pei_data.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -32,5 +34,3 @@
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-verstage-y += car.c
diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/google/lars/bootblock_mainboard.c
similarity index 87%
copy from src/mainboard/google/chell/car.c
copy to src/mainboard/google/lars/bootblock_mainboard.c
index 7791b92..d5146224 100644
--- a/src/mainboard/google/chell/car.c
+++ b/src/mainboard/google/lars/bootblock_mainboard.c
@@ -13,20 +13,20 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
+ * which it shouldn't do. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
-void car_mainboard_post_console_init(void)
+void bootblock_mainboard_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
diff --git a/src/mainboard/google/lars/car.c b/src/mainboard/google/lars/car.c
deleted file mode 100644
index 7791b92..0000000
--- a/src/mainboard/google/lars/car.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void car_mainboard_post_console_init(void)
-{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
- early_config_gpio();
-}
diff --git a/src/mainboard/intel/kunimitsu/Makefile.inc b/src/mainboard/intel/kunimitsu/Makefile.inc
index 4bf6e0a..cafa12c 100644
--- a/src/mainboard/intel/kunimitsu/Makefile.inc
+++ b/src/mainboard/intel/kunimitsu/Makefile.inc
@@ -16,10 +16,12 @@
subdirs-y += spd
+bootblock-y += bootblock_mainboard.c
+
romstage-y += boardid.c
-romstage-y += car.c
romstage-y += pei_data.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -32,5 +34,3 @@
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-
-verstage-y += car.c
diff --git a/src/mainboard/google/chell/car.c b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c
similarity index 87%
copy from src/mainboard/google/chell/car.c
copy to src/mainboard/intel/kunimitsu/bootblock_mainboard.c
index 7791b92..d5146224 100644
--- a/src/mainboard/google/chell/car.c
+++ b/src/mainboard/intel/kunimitsu/bootblock_mainboard.c
@@ -13,20 +13,20 @@
* GNU General Public License for more details.
*/
+#include <bootblock_common.h>
#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
#include <soc/gpio.h>
#include "gpio.h"
static void early_config_gpio(void)
{
/* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
+ * which it shouldn't do. We have to prepare certain gpios here
* because of the brokenness in FSP. */
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
}
-void car_mainboard_post_console_init(void)
+void bootblock_mainboard_init(void)
{
/* Ensure the EC and PD are in the right mode for recovery */
google_chromeec_early_init();
diff --git a/src/mainboard/intel/kunimitsu/car.c b/src/mainboard/intel/kunimitsu/car.c
deleted file mode 100644
index 7791b92..0000000
--- a/src/mainboard/intel/kunimitsu/car.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <ec/google/chromeec/ec.h>
-#include <fsp/car.h>
-#include <soc/gpio.h>
-#include "gpio.h"
-
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
-void car_mainboard_post_console_init(void)
-{
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
- early_config_gpio();
-}