nb/intel/sandybridge: add and use memory thermal configuration registers
Change-Id: I96efeadcc7d22bc8453645f6a0884d82edf3aec6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4e42c71..3cc9d29 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -3164,9 +3164,9 @@
}
}
- MCHBAR32(0x5880) = 0xca9171e5;
- MCHBAR32_AND_OR(0x5888, ~0xffffff, 0xe4d5d0);
- MCHBAR32_AND(0x58a8, ~0x1f);
+ MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5;
+ MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0xffffff, 0xe4d5d0);
+ MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f);
FOR_ALL_CHANNELS
MCHBAR32_AND_OR(TC_RFP_C0 + 0x400 * channel, ~0x30000, 1 << 16);
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 6dcb3ce..725cc04 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -137,6 +137,9 @@
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
#define MAD_DIMM_CH0 0x5004 /* Address Decode Channel 0 */
#define MAD_DIMM_CH1 0x5008 /* Address Decode Channel 1 */
+#define MEM_TRML_ESTIMATION_CONFIG 0x5880
+#define MEM_TRML_THRESHOLDS_CONFIG 0x5888
+#define MEM_TRML_INTERRUPT 0x58a8
#define MC_BIOS_REQ 0x5e00
#define MC_BIOS_DATA 0x5e04
#define SSKPD 0x5d14 /* 16bit (scratchpad) */