diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 02799d3..2322097 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -35,7 +35,7 @@
 }
 
 /*
- * TODO: We could determine how many PCIe busses we need in the bar.
+ * TODO: We could determine how many PCIe buses we need in the bar.
  *       For now, that number is hardcoded to a max of 64.
  */
 static struct device_operations pci_domain_ops = {
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 51ee320..ac19fcc 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -63,7 +63,7 @@
 config CHECK_SLFRCS_ON_RESUME
 	def_bool n
 	help
-	  On some boards it may be neccessary to hard reset early
+	  On some boards it may be necessary to hard reset early
 	  during resume from S3 if the SLFRCS register indicates that
 	  a memory channel is not guaranteed to be in self-refresh.
 	  On other boards the check always creates a false positive,
diff --git a/src/northbridge/intel/ironlake/bootblock.c b/src/northbridge/intel/ironlake/bootblock.c
index 6610a3e..241eb43 100644
--- a/src/northbridge/intel/ironlake/bootblock.c
+++ b/src/northbridge/intel/ironlake/bootblock.c
@@ -22,7 +22,7 @@
 {
 	/*
 	 * The QuickPath bus number is the topmost bus number, as per the value
-	 * of the SAD_PCIEXBAR register. The register defaults to 256 busses on
+	 * of the SAD_PCIEXBAR register. The register defaults to 256 buses on
 	 * reset. Thus, hardcode the bus number when first setting up PCIEXBAR.
 	 */
 	const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 4b5f2b3..9ef491b 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -2437,7 +2437,7 @@
 	if (enable_iosav_opt)
 		mchbar_write32(MCMNTS_SPARE, 1);
 
-	printram("Aggresive write training:\n");
+	printram("Aggressive write training:\n");
 
 	for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) {
 		FOR_ALL_POPULATED_CHANNELS {