mb/google/rex/variants/ovis: Add USB and TCSS configuration
+-------------+----------------+------------+---------------------------------+
| PCH USB 2.0 | Connector Type | OC Mapping | Remarks |
+-------------+----------------+------------+---------------------------------+
| 1 | Type-C | OC_0 | Type C port - TCP1 |
| 2 | Type-C | OC_0 | Type C port - TCP0 |
| 3 | Type-C | OC_0 | Type C port - TCP2 |
| 4 | Type-A | OC_3 | USB3.2 Gen2x1 Type-A Port – TAP0|
| 7 | Type-A | OC_3 | TAP1 |
| 8 | Type-A | OC_3 | TAP2 |
| 9 | Type-A | OC_3 | TAP3 |
+-------------+----------------+------------+---------------------------------+
+---------------------+-------------------+------------+---------+
| PCH USB 3.1 Gen 2x1 | Connector Details | OC Mapping | Remarks |
+---------------------+-------------------+------------+---------+
| 1 | Type-A | OC_3 | TAP0 |
| 2 | Type-A | OC_3 | TAP1 |
+---------------------+-------------------+------------+---------+
+------+-------------------+------------+-----------------------------+
| TCPx | Connector Details | OC Mapping | Remarks |
+------+-------------------+------------+-----------------------------+
| 1 | Type C port 0 | OC_0 | To onboard Type-C connector |
| 2 | Type C port 1 | OC_0 | To onboard Type-C connector |
| 3 | Type C port 2 | OC_0 | To onboard Type-C connector |
+------+-------------------+------------+-----------------------------+
BUG=b:274421383
TEST=util/abuild/abuild -p none -t google/rex -x -a -b ovis
Change-Id: Icc81f12ec6cc4af37bcc1fcf3164cbfa5612a443
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
diff --git a/src/mainboard/google/rex/variants/ovis/overridetree.cb b/src/mainboard/google/rex/variants/ovis/overridetree.cb
index 058a240..889ae0e 100644
--- a/src/mainboard/google/rex/variants/ovis/overridetree.cb
+++ b/src/mainboard/google/rex/variants/ovis/overridetree.cb
@@ -1,4 +1,18 @@
chip soc/intel/meteorlake
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0
+ register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # Type-A Port A0
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" # Type-A Port A1
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" # Type-A Port A2
+ register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A3
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type-A Port A1
+
+ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
+ register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
+ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)"
register "serial_io_i2c_mode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
@@ -36,6 +50,128 @@
.flags = PCIE_RP_LTR | PCIE_RP_AER,
}"
end # PCIE11 SSD card
+ device ref tbt_pcie_rp0 on end
+ device ref tbt_pcie_rp1 on end
+ device ref tbt_pcie_rp2 on end
+ device ref tcss_xhci on
+ chip drivers/usb/acpi
+ device ref tcss_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C0""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+ device ref tcss_usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref tcss_usb3_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-C Port C2""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ device ref tcss_usb3_port3 on end
+ end
+ end
+ end
+ end
+ device ref tcss_dma0 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+ use tcss_usb3_port1 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ chip drivers/intel/usb4/retimer
+ register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+ use tcss_usb3_port2 as dfp[1].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref tcss_dma1 on
+ chip drivers/intel/usb4/retimer
+ register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
+ use tcss_usb3_port3 as dfp[0].typec_port
+ device generic 0 on end
+ end
+ end
+ device ref xhci on
+ chip drivers/usb/acpi
+ device ref xhci_root_hub on
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C0""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, CENTER, ACPI_PLD_GROUP(1, 1))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER"
+ device ref usb2_port2 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C1""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
+ device ref usb2_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-C Port C2""
+ register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(1, 2))"
+ device ref usb2_port3 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A0""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb2_port4 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A1""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+ device ref usb2_port7 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A2""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(3, 3))"
+ device ref usb2_port8 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB2 Type-A Port A3""
+ register "type" = "UPC_TYPE_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(3, 4))"
+ device ref usb2_port9 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A0""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))"
+ device ref usb3_port1 on end
+ end
+ chip drivers/usb/acpi
+ register "desc" = ""USB3 Type-A Port A1""
+ register "type" = "UPC_TYPE_USB3_A"
+ register "use_custom_pld" = "true"
+ register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 2))"
+ register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER"
+ device ref usb3_port2 on end
+ end
+ end
+ end
+ end
device ref i2c4 on
chip drivers/i2c/tpm
register "hid" = ""GOOG0005""
@@ -45,8 +181,32 @@
end
device ref soc_espi on
chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
+ use conn2 as mux_conn[2]
device pnp 0c09.0 on end
end
end
+ device ref pmc hidden
+ chip drivers/intel/pmc_mux
+ device generic 0 on
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port2 as usb2_port
+ use tcss_usb3_port1 as usb3_port
+ device generic 0 alias conn0 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port1 as usb2_port
+ use tcss_usb3_port2 as usb3_port
+ device generic 1 alias conn1 on end
+ end
+ chip drivers/intel/pmc_mux/conn
+ use usb2_port3 as usb2_port
+ use tcss_usb3_port3 as usb3_port
+ device generic 2 alias conn2 on end
+ end
+ end
+ end
+ end
end
end