mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
index 0d0e829..57710c2 100644
--- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
+++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb
@@ -255,15 +255,15 @@
# See AMD 55570-B1 Table 13: PCI Device ID Assignments.
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 0.2 on end # IOMMU
- device pci 1.2 on # GPP Bridge 1 - Wifi
+ device ref iommu on end
+ device ref gpp_bridge_1 on # Wifi
chip drivers/wifi/generic
register "wake" = "GEVENT_8"
device pci 00.0 on end
end
end
- device pci 1.3 on end # GPP Bridge 2 - SD
- device pci 8.1 on # Internal GPP Bridge 0 to Bus A
+ device ref gpp_bridge_2 on end # SD
+ device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@@ -353,7 +353,7 @@
device pci 0.6 off end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 14.3 on # - D14F3 bridge
+ device ref lpc_bridge on
chip ec/google/chromeec
device pnp 0c09.0 on
chip ec/google/chromeec/i2c_tunnel