mainboards using soc/amd/picasso: use aliases for PCIe devices on bus 0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia6199c70163d32467abe5ba5da55c73ff62ba10f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb
index 7015185..10a5d2e 100644
--- a/src/mainboard/amd/bilby/devicetree.cb
+++ b/src/mainboard/amd/bilby/devicetree.cb
@@ -140,11 +140,11 @@
device domain 0 on
subsystemid 0x1022 0x1510 inherit
- device pci 0.2 on end # IOMMU
- device pci 1.1 on end # GPP Bridge 0
- device pci 1.2 on end # GPP Bridge 1
- device pci 1.5 on end # NVMe
- device pci 8.1 on # Bridge to Bus A
+ device ref iommu on end
+ device ref gpp_bridge_0 on end
+ device ref gpp_bridge_1 on end
+ device ref gpp_bridge_4 on end # NVMe
+ device ref internal_bridge_a on
device pci 0.0 on end # Internal GPU
device pci 0.1 on end # Display HDA
device pci 0.2 on end # Crypto Coprocessor
@@ -154,12 +154,12 @@
device pci 0.6 on end # HDA
device pci 0.7 on end # non-Sensor Fusion Hub device
end
- device pci 8.2 on # Bridge to Bus B
+ device ref internal_bridge_b on
device pci 0.0 off end # AHCI
device pci 0.1 off end # integrated Ethernet MAC
device pci 0.2 off end # integrated Ethernet MAC
end
- device pci 14.3 on # D14F3 bridge
+ device ref lpc_bridge on
chip superio/smsc/sio1036 # optional debug card
end
end