tree 7f0dccd2614bb5641636580613a957d0d525c02f
parent 9207621d23aefe7213ab1a764bd78402237e4e8f
author Won Chung <wonchung@google.com> 1710889284 +0000
committer Felix Held <felix-coreboot@felixheld.de> 1714994522 +0000

mb/google/brya: Correct _PLD values

For Mithrax and Felwinter, port C1 is on the left side and port C2 is on
the right side. Correct the values accordingly.

The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.

BUG=b:321051330
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT

Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>