mb/google/poppy/variants/nocturne: enable FPMCU power
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 235391e..9d9c5ae 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -423,15 +423,8 @@
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"
register "wake" = "GPE0_DW0_09" # GPP_C9
- register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
- register "reset_delay_ms" = "0"
- register "reset_off_delay_ms" = "0"
- register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
- register "enable_delay_ms" = "0"
- register "enable_off_delay_ms" = "0"
- register "has_power_resource" = "1"
device spi 0 on end
- end
+ end # FPMCU
end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO