tree 6043754fd186e18192ab5aad4218d1b79e0fe7b4
parent 7c276c0dd74623bc9e11584f3fb74e876823af9f
author Werner Zeh <werner.zeh@siemens.com> 1573203020 +0100
committer Patrick Georgi <pgeorgi@google.com> 1573468495 +0000

mb/siemens/mc_apl6: Adjust clock lines used on PCIe-2-PCI bridge

On this mainboard variant the PCIe-2-PCI bridge is used a bit different.
Adjust the switched off clock lines to match the mainboard
configuration.

Change-Id: I16f3b6eed0948c8201baecdfbb8052c6c1c335c8
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>