tree fadca287414f948d07ff2f05983949e8850d4aa4
parent 5d0893adced0423241dc016392ca9d4ce1340b2e
author Raul E Rangel <rrangel@chromium.org> 1591914469 -0600
committer Patrick Georgi <pgeorgi@google.com> 1592153578 +0000

soc/amd/picasso: Explicitly disable legacy UART

The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.

Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.

Before the change you would see the following in the console:
[    0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A

After this change, we no longer see it.

BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>