commit 4eee50642ff5ac6e7d7830afd38693943fe17b5b
author Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Fri Jun 02 13:06:06 2023 +0800
committer Felix Held <felix-coreboot@felixheld.de> Wed Jun 21 13:31:34 2023 +0000
tree 8468375914af28a58212828682c8125b88abed16
parent 3ea0202925a9535ca58184cfad736122c97e4d41

mb/google/rex/var/screebo: set HBR smbus pin as NC

Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case it prevents ese and cse from entering suspend.

BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.

Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/rex/variants/screebo/gpio.c

diff --git a/src/mainboard/google/rex/variants/screebo/gpio.c b/src/mainboard/google/rex/variants/screebo/gpio.c
index a9d4593..3fb71fb 100644
--- a/src/mainboard/google/rex/variants/screebo/gpio.c
+++ b/src/mainboard/google/rex/variants/screebo/gpio.c
@@ -102,9 +102,9 @@
 	/* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */
 	PAD_NC(GPP_C02, NONE),
 	/* GPP_C03 : [] ==> SOC_TCP_SMBUS_CLK*/
-	PAD_CFG_NF_LOCK(GPP_C03, NONE, NF1, LOCK_CONFIG),
+	PAD_NC(GPP_C03, NONE),
 	/* GPP_C04 : [] ==> SOC_TCP_SMBUS_SDA*/
-	PAD_CFG_NF_LOCK(GPP_C04, NONE, NF1, LOCK_CONFIG),
+	PAD_NC(GPP_C04, NONE),
 	/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
 	PAD_NC(GPP_C05, NONE),
 	/* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */