commit 4ee83b2f9435fe08cb73ba818b567597cafd973d
author Marshall Dawson <marshalldawson3rd@gmail.com> Fri May 03 11:44:22 2019 -0600
committer Martin Roth <martinroth@google.com> Thu Jun 06 18:51:03 2019 +0000
tree 3a0d2a58b62ac87d990703926aaf82d8347d5d49
parent 3ce0360592f036ce586a49db84146d435a23e662

soc/amd/stoneyridge: Relocate MMIO access of ACPI registers

The AcpiMmio block allowing direct access to the ACPI registers
has remained consistent across AMD models.  Move the support from
soc//stoneyridge to soc//common.

BUG=b:131682806

Change-Id: I0e017a71f8efb4b614986cb327de398644599853
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32655
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/stoneyridge/acpi.c

diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 2cd9632..d1ea24f 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -29,6 +29,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <amdblocks/acpimmio.h>
+#include <amdblocks/acpi.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
@@ -99,7 +100,7 @@
 		fadt->s4bios_req = 0;	/* Not supported */
 		fadt->pstate_cnt = 0;	/* Not supported */
 		fadt->cst_cnt = 0;	/* Not supported */
-		acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 0); /* clear SCI_EN */
+		acpi_disable_sci();
 	} else {
 		fadt->smi_cmd = 0;	/* disable system management mode */
 		fadt->acpi_enable = 0;	/* unused if SMI_CMD = 0 */
@@ -107,7 +108,7 @@
 		fadt->s4bios_req = 0;	/* unused if SMI_CMD = 0 */
 		fadt->pstate_cnt = 0;	/* unused if SMI_CMD = 0 */
 		fadt->cst_cnt = 0x00;	/* unused if SMI_CMD = 0 */
-		acpi_write32(MMIO_ACPI_PM1_CNT_BLK, 1); /* set SCI_EN */
+		acpi_enable_sci();
 	}
 
 	fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK;