broadwell: Change all SoC headers to <soc/headername.h> system
This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c
index b6c0f9a..2df32a9 100644
--- a/src/mainboard/intel/wtm2/acpi_tables.c
+++ b/src/mainboard/intel/wtm2/acpi_tables.c
@@ -29,8 +29,8 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <cpu/cpu.h>
-#include <broadwell/acpi.h>
-#include <broadwell/nvs.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
#include "thermal.h"
void acpi_create_gnvs(global_nvs_t *gnvs)
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index fe469f7..b240b84 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -22,7 +22,7 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
/* Compile-time settings for developer and recovery mode. */
#define DEV_MODE_SETTING 1
diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c
index a8811d2..a876e1f 100644
--- a/src/mainboard/intel/wtm2/fadt.c
+++ b/src/mainboard/intel/wtm2/fadt.c
@@ -18,7 +18,7 @@
*/
#include <string.h>
-#include <broadwell/acpi.h>
+#include <soc/acpi.h>
void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
{
diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h
index 47272b8..f4825ba 100644
--- a/src/mainboard/intel/wtm2/gpio.h
+++ b/src/mainboard/intel/wtm2/gpio.h
@@ -20,7 +20,7 @@
#ifndef INTEL_WTM2_GPIO_H
#define INTEL_WTM2_GPIO_H
-#include <broadwell/gpio.h>
+#include <soc/gpio.h>
static const struct gpio_config mainboard_gpio_config[] = {
PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */
diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c
index bec0b61..1c4edef 100644
--- a/src/mainboard/intel/wtm2/mainboard_smi.c
+++ b/src/mainboard/intel/wtm2/mainboard_smi.c
@@ -20,8 +20,8 @@
#include <arch/io.h>
#include <console/console.h>
#include <cpu/x86/smm.h>
-#include <broadwell/nvs.h>
-#include <broadwell/smm.h>
+#include <soc/nvs.h>
+#include <soc/smm.h>
int mainboard_io_trap_handler(int smif)
{
diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c
index e67d8e5..f77895a 100644
--- a/src/mainboard/intel/wtm2/pei_data.c
+++ b/src/mainboard/intel/wtm2/pei_data.c
@@ -20,9 +20,9 @@
#include <stdint.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
void mainboard_fill_pei_data(struct pei_data *pei_data)
{
diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c
index 41bef93..d3ec418 100644
--- a/src/mainboard/intel/wtm2/romstage.c
+++ b/src/mainboard/intel/wtm2/romstage.c
@@ -21,10 +21,10 @@
#include <console/console.h>
#include <stdint.h>
#include <string.h>
-#include <broadwell/gpio.h>
-#include <broadwell/pei_data.h>
-#include <broadwell/pei_wrapper.h>
-#include <broadwell/romstage.h>
+#include <soc/gpio.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include <soc/romstage.h>
#include "gpio.h"
void mainboard_romstage_entry(struct romstage_params *rp)