tree dca773b9eff205c27c489ca31e98b3f5016837df
parent bd0fa62b6be176395dc119099236709e52a6203e
author Eric Lai <ericr_lai@compal.corp-partner.google.com> 1608541069 +0800
committer Tim Wawrzynczak <twawrzynczak@chromium.org> 1609262727 +0000

soc/intel/alderlake: Update chipset.cb for TCSS and USB

Follow TGL chipset.cb to add alias for TCSS and USB ports.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>