# SPDX-License-Identifier: GPL-2.0-only

config SOC_INTEL_QUARK
	bool
	help
	  Intel Quark support

if SOC_INTEL_QUARK

config CPU_SPECIFIC_OPTIONS
	def_bool y
	select ARCH_X86
	select NO_ECAM_MMCONF_SUPPORT
	select REG_SCRIPT
	select PLATFORM_USES_FSP2_0
	select SOC_INTEL_COMMON
	select SOC_INTEL_COMMON_RESET
	select SOC_SETS_MSRS
	select SPI_FLASH
	select UART_OVERRIDE_REFCLK
	select UDELAY_TSC
	select TSC_MONOTONIC_TIMER
	select UNCOMPRESSED_RAMSTAGE
	select USE_MARCH_586
	select NO_SMM

#####
# Debug serial output
#     The following options configure the debug serial port
#####

config ENABLE_BUILTIN_HSUART0
	bool "Enable built-in HSUART0"
	default n
	select NO_UART_ON_SUPERIO
	select DRIVERS_UART_8250MEM_32
	help
	  The Quark SoC has two HSUART. Choose this option to configure the pads
	  and enable HSUART0, which can be used for the debug console.

config ENABLE_BUILTIN_HSUART1
	bool "Enable built-in HSUART1"
	default n
	depends on ! ENABLE_BUILTIN_HSUART0
	select NO_UART_ON_SUPERIO
	select DRIVERS_UART_8250MEM_32
	help
	  The Quark SoC has two HSUART. Choose this option to configure the pads
	  and enable HSUART1, which can be used for the debug console.

config TTYS0_BASE
	hex "HSUART Base Address"
	default 0xA0019000
	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1
	help
	  Memory mapped MMIO of HSUART.

config TTYS0_LCS
	int
	default 3
	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1

# Console: PCI UART bus 0 << 20, device 20 << 15, function x << 12
#          Valid bit, PCI UART in use: 1 << 31
config UART_PCI_ADDR
	hex
	default 0x800a1000 if ENABLE_BUILTIN_HSUART0
	default 0x800a5000 if ENABLE_BUILTIN_HSUART1
	depends on ENABLE_BUILTIN_HSUART0 || ENABLE_BUILTIN_HSUART1

#####
# Debug support
#     The following options provide debug support for the Quark coreboot
#     code.  The SD LED is used as a binary marker to determine if a
#     specific point in the execution flow has been reached.
#####

config ENABLE_DEBUG_LED
	bool
	default n
	help
	  Enable the use of the SD LED for early debugging before serial output
	  is available.  Setting this LED indicates that control has reached the
	  desired check point.

config ENABLE_DEBUG_LED_ESRAM
	bool "SD LED indicates ESRAM initialized"
	default n
	select ENABLE_DEBUG_LED
	help
	  Indicate that ESRAM has been successfully initialized.  If the SD LED
	  does not light then the ESRAM initialization needs to be debugged.

config ENABLE_DEBUG_LED_BOOTBLOCK_ENTRY
	bool "SD LED indicates bootblock.c successfully entered"
	default n
	select ENABLE_DEBUG_LED
	help
	  Indicate that bootblock_c_entry was entered.  If the SD LED does not
	  light then debug the code between ESRAM and bootblock_c_entry.

config ENABLE_DEBUG_LED_SOC_EARLY_INIT_ENTRY
	bool "SD LED indicates bootblock_soc_early_init successfully entered"
	default n
	select ENABLE_DEBUG_LED
	help
	  Indicate that bootblock_soc_early_init was entered.  If the SD LED
	  does not light then debug the code in bootblock_main_with_timestamp.

config ENABLE_DEBUG_LED_SOC_EARLY_INIT_EXIT
	bool "SD LED indicates bootblock_soc_early_init successfully exited"
	default n
	select ENABLE_DEBUG_LED
	help
	  Indicate that bootblock_soc_early_init exited.  If the SD LED does not
	  light then debug the scripts in bootblock_soc_early_init.

config ENABLE_DEBUG_LED_SOC_INIT_ENTRY
	bool "SD LED indicates bootblock_soc_init successfully entered"
	default n
	select ENABLE_DEBUG_LED
	help
	  Indicate that bootblock_soc_init was entered.  If the SD LED does not
	  light then debug the code in bootblock_mainboard_early_init and
	  console_init.  If the SD LED does light but there is no serial then
	  debug the serial port configuration and initialization.

#####
# ESRAM layout
#     Specify the portion of the ESRAM for coreboot to use as its data area.
#####

config DCACHE_RAM_BASE
	hex
	default 0x80000000

config DCACHE_RAM_SIZE
	hex
	default 0x40000

config DISPLAY_ESRAM_LAYOUT
	bool "Display ESRAM layout"
	default n
	help
	  Select this option to display coreboot's use of ESRAM.

#####
# Flash layout
#     Specify the size of the coreboot file system in the read-only
#     (recovery) portion of the flash part.
#####

config CBFS_SIZE
	default 0x200000
	help
	  Specify the size of the coreboot file system in the read-only (recovery)
	  portion of the flash part.  On Quark systems the firmware image stores
	  more than just coreboot, including:
	   - The chipset microcode (RMU) binary file located at 0xFFF00000
	   - Intel Trusted Execution Engine firmware

#####
# FSP binary
#     The following options control the FSP binary file placement in
#     the flash image and ESRAM.  This file is required by the Quark
#     SoC code to boot coreboot and its payload.
#####

config FSP_ESRAM_LOC
	hex
	default 0x80040000
	help
	  The location in ESRAM where a copy of the FSP binary is placed.

config FSP_M_FILE
	string
	default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_M.fd"

config FSP_S_FILE
	string
	default "3rdparty/blobs/soc/intel/quark/\$(CONFIG_FSP_TYPE)/\$(CONFIG_FSP_BUILD_TYPE)/FSP_S.fd"

#####
# RMU binary
#     The following options control the Quark chipset microcode file
#     placement in the flash image.  This file is required to bring
#     the Quark processor out of reset.
#####

config ADD_RMU_FILE
	bool "Should the RMU binary be added to the flash image?"
	default n
	help
	  The RMU file is required to get the chip out of reset.

config RMU_FILE
	string
	default "3rdparty/blobs/soc/intel/quark/rmu.bin"
	depends on ADD_RMU_FILE
	help
	  The path and filename of the Intel Quark RMU binary.

config RMU_LOC
	hex
	default 0xfff00000
	depends on ADD_RMU_FILE
	help
	  The location in CBFS that the RMU is located. It must match the
	  strap-determined base address.

config DCACHE_BSP_STACK_SIZE
	hex
	default 0x4000

#####
# Test support
#####

config STORAGE_TEST
	bool "Test SD/MMC/eMMC card or device access"
	default n
	select COMMONLIB_STORAGE
	select SDHCI_CONTROLLER
	help
	  Read block 0 from each partition of the storage device.  User
	  must also enable one or both of COMMONLIB_STORAGE_SD or
	  COMMONLIB_STORAGE_MMC.

config STORAGE_LOG
	bool "Log and display SD/MMC commands"
	default n
	depends on STORAGE_TEST

#####
# I2C debug support
#####

config I2C_DEBUG
	bool "Enable I2C debugging"
	default n
	help
	  Display the I2C segments and controller errors

endif # SOC_INTEL_QUARK