tree 6c6f8f44ae566505f53bf00afc5f13ca8c7cfc04
parent c4ed1e82bb0de8c413f164c2d5a1f82173d5c580
author garmin chang <garmin.chang@mediatek.corp-partner.google.com> 1654669258 +0800
committer Felix Held <felix-coreboot@felixheld.de> 1657708837 +0000

soc/mediatek/mt8188: Add PLL and clock init support

Add PLL and clock init code, frequency meter and APIs for raising little
CPU/CCI frequency.

For usb clock setting, we also implement mt_pll_usb_clock_setting() to
enable usb clock for all ports.

TEST=build pass
BUG=b:233720142

Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I03cb5a4c6fa5ddad7da6f955d0c6d0b3395503e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>