{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc
index 93f3b59..10877b9 100644
--- a/src/drivers/intel/fsp1_1/Makefile.inc
+++ b/src/drivers/intel/fsp1_1/Makefile.inc
@@ -21,6 +21,7 @@
verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c
bootblock-y += bootblock.c
+bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
bootblock-y += fsp_util.c
romstage-y += car.c
@@ -42,8 +43,6 @@
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
-cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
-
postcar-y += stage_cache.c
ifneq ($(CONFIG_SKIP_FSP_CAR),y)
postcar-y += temp_ram_exit.c
diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.S
similarity index 93%
rename from src/drivers/intel/fsp1_1/cache_as_ram.inc
rename to src/drivers/intel/fsp1_1/cache_as_ram.S
index 493dbc8..3460b9d 100644
--- a/src/drivers/intel/fsp1_1/cache_as_ram.inc
+++ b/src/drivers/intel/fsp1_1/cache_as_ram.S
@@ -5,6 +5,7 @@
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018-2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,6 +17,8 @@
* GNU General Public License for more details.
*/
+#include <cpu/x86/post_code.h>
+
/*
* Replacement for cache_as_ram.inc when using the FSP binary. This code
* locates the FSP binary, initializes the cache as RAM and performs the
@@ -24,8 +27,10 @@
* performs the final stage of initialization.
*/
-/* I/O delay between post codes on failure */
-#define LHLT_DELAY 0x50000
+#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
+
+.global bootblock_pre_c_entry
+bootblock_pre_c_entry:
/*
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
@@ -129,10 +134,9 @@
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
- subl $4, %esp
+ subl $8, %esp
- /* Push BIST and initial timestamp on the stack */
- pushl %ebx /* bist */
+ /* Push initial timestamp on the stack */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
movd %mm0, %eax
@@ -141,12 +145,10 @@
before_romstage:
post_code(0x2A)
- /* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
- in cpu/intel/car/romstage.c */
- call bootblock_c_entry_bist
+ /* Call bootblock_c_entry(uint64_t base_timestamp) */
+ call bootblock_c_entry
- movb $0x69, %ah
- jmp .Lhlt
+ /* Never reached */
halt1:
/*
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index dd1766403..67ed099 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -101,18 +101,6 @@
* is still enabled. We can directly access work buffer here. */
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
- if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) {
- /* Call into pre-console init code then initialize console. */
- car_soc_pre_console_init();
- car_mainboard_pre_console_init();
- console_init();
-
- display_mtrrs();
-
- car_soc_post_console_init();
- car_mainboard_post_console_init();
- }
-
if (prog_locate(&fsp))
die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");
@@ -125,19 +113,3 @@
cache_as_ram_stage_main(fih);
}
-
-void __weak car_mainboard_pre_console_init(void)
-{
-}
-
-void __weak car_soc_pre_console_init(void)
-{
-}
-
-void __weak car_mainboard_post_console_init(void)
-{
-}
-
-void __weak car_soc_post_console_init(void)
-{
-}
diff --git a/src/drivers/intel/fsp1_1/include/fsp/car.h b/src/drivers/intel/fsp1_1/include/fsp/car.h
index 8d7a683..3d99fa6 100644
--- a/src/drivers/intel/fsp1_1/include/fsp/car.h
+++ b/src/drivers/intel/fsp1_1/include/fsp/car.h
@@ -24,12 +24,4 @@
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
void cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
-
-/* Mainboard and SoC initialization prior to console. */
-void car_mainboard_pre_console_init(void);
-void car_soc_pre_console_init(void);
-/* Mainboard and SoC initialization post console initialization. */
-void car_mainboard_post_console_init(void);
-void car_soc_post_console_init(void);
-
#endif