add intel speedstep support and some PM fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 136f563..3d1d9d2 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -20,7 +20,13 @@
*/
#include <arch/asm.h>
-#include "../../../../src/northbridge/intel/i945/ich7.h"
+
+// Make sure no stage 2 code is included:
+#define __ROMCC__
+
+// FIXME: Is this piece of code southbridge specific, or
+// can it be cleaned up so this include is not required?
+#include "../../../southbridge/intel/i82801gx/i82801gx.h"
#undef DEBUG_SMM_RELOCATION
//#define DEBUG_SMM_RELOCATION