mb/lenovo/x220: Allow optional use of the mrc.bin
Besides the FSP codepath, Sandy Bridge has two codepaths, one native
and one in the form of a binary. This allows the use of the binary.
This can be useful to find flaws in the native raminit.
The native raminit is still selected by default.
Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index bdd251a..e38dfe7 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -27,6 +27,7 @@
#include <arch/acpi.h>
#include <console/console.h>
#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h>
@@ -53,6 +54,55 @@
RCBA32(BUC) = 0;
}
+void mainboard_fill_pei_data(struct pei_data *pei_data)
+{
+ struct pei_data pei_data_template = {
+ .pei_version = PEI_VERSION,
+ .mchbar = (uintptr_t)DEFAULT_MCHBAR,
+ .dmibar = (uintptr_t)DEFAULT_DMIBAR,
+ .epbar = DEFAULT_EPBAR,
+ .pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
+ .smbusbar = SMBUS_IO_BASE,
+ .wdbbar = 0x4000000,
+ .wdbsize = 0x1000,
+ .hpet_address = CONFIG_HPET_ADDRESS,
+ .rcba = (uintptr_t)DEFAULT_RCBABASE,
+ .pmbase = DEFAULT_PMBASE,
+ .gpiobase = DEFAULT_GPIOBASE,
+ .thermalbase = 0xfed08000,
+ .system_type = 0, // 0 Mobile, 1 Desktop/Server
+ .tseg_size = CONFIG_SMM_TSEG_SIZE,
+ .spd_addresses = { 0xa0, 0x00,0xa2,0x00 },
+ .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
+ .ec_present = 1,
+ .gbe_enable = 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ .dimm_channel0_disabled = 2,
+ .dimm_channel1_disabled = 2,
+ .max_ddr3_freq = 1333,
+ .usb_port_config = {
+ { 1, 0, 0x0040 },
+ { 1, 1, 0x0080 },
+ { 1, 3, 0x0080 },
+ { 1, 3, 0x0080 },
+ { 1, 0, 0x0080 },
+ { 1, 0, 0x0080 },
+ { 1, 2, 0x0040 },
+ { 1, 2, 0x0040 },
+ { 1, 6, 0x0080 },
+ { 1, 5, 0x0080 },
+ { 1, 6, 0x0080 },
+ { 1, 6, 0x0080 },
+ { 1, 7, 0x0080 },
+ { 1, 6, 0x0080 },
+ },
+ };
+ *pei_data = pei_data_template;
+}
+
const struct southbridge_usb_port mainboard_usb_ports[] = {
{ 1, 0, 0 },
{ 1, 1, 1 },
@@ -83,3 +133,8 @@
void mainboard_config_superio(void)
{
}
+
+int mainboard_should_reset_usb(int s3resume)
+{
+ return !s3resume;
+}