soc/intel/cmn/pch/lockdown: Implement LPC lock down configuration
This patch implements a helper function to perform LPC registers lock
down configuration.
BUG=b:211954778
TEST=Able to build and boot google/redrix to OS. Verified LPC PCI
configuration register offset 0xDC bits BILD and LE are set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e49b783e5db0ff40238e6e9259e48a4ecca66f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c
index 8032b4a..cd8b402 100644
--- a/src/soc/intel/common/pch/lockdown/lockdown.c
+++ b/src/soc/intel/common/pch/lockdown/lockdown.c
@@ -3,6 +3,7 @@
#include <bootstate.h>
#include <intelblocks/cfg.h>
#include <intelblocks/fast_spi.h>
+#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelpch/lockdown.h>
#include <intelblocks/gpmr.h>
@@ -88,6 +89,24 @@
}
}
+static void lpc_lockdown_config(int chipset_lockdown)
+{
+ /* Set BIOS Interface Lock, BIOS Lock */
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) {
+ /* BIOS Interface Lock */
+ lpc_set_bios_interface_lock_down();
+
+ /* Only allow writes in SMM */
+ if (CONFIG(BOOTMEDIA_SMM_BWP)) {
+ lpc_set_eiss();
+ lpc_enable_wp();
+ }
+
+ /* BIOS Lock */
+ lpc_set_lock_enable();
+ }
+}
+
/*
* platform_lockdown_config has 2 major part.
* 1. Common SoC lockdown configuration.
@@ -102,6 +121,9 @@
/* SPI lock down configuration */
fast_spi_lockdown_cfg(chipset_lockdown);
+ /* LPC/eSPI lock down configuration */
+ lpc_lockdown_config(chipset_lockdown);
+
/* DMI lock down configuration */
lockdown_cfg();