| commit | e07df9d78351cda0818309fc7f3e78d8057d421e | [log] [tgz] |
|---|---|---|
| author | Arthur Heymans <arthur@aheymans.xyz> | Mon Apr 09 22:03:21 2018 +0200 |
| committer | Patrick Georgi <pgeorgi@google.com> | Thu Jun 07 06:41:47 2018 +0000 |
| tree | 616c616cfa71664b43bee0ceab9749481637fdc9 | |
| parent | a16cffe480f0e4ce8da28e2893d27f012963ab5a [diff] |
nb/intel/i945: Enable and allocate 8M for TSEG TSEG can be used as a stage cache and SMM can be relocated here. Tested on Intel D945GCLF, still boots. Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/25592 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>